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Intel To Produce 65-Nanometer Chips In 2005

Posted by ryuzaki0 on from the including-prince's-wardrobe dept.

Ridgelift writes "In keeping with Moore's Law, Intel will begin mass-producing chips using 65-nanometer process technology in 2005, according to a ZDNet article (additional coverage at EE Times and The Inquirer). Intel recently produced a Static Random Access Memory (SRAM) cell at 0.57 square microns, in comparison to 90-nanometer process measuring 1 square micron. "You can get a 40 to 50 percent increase in clock speed with no further improvements" says Intel director Mark Bohr."

5 of 187 comments (clear)

  1. Reduce Power? by brandido · · Score: 4, Interesting
    According to the article,
    Reducing the size of the chip improves performance, reduces costs and can potentially cut energy consumption. In a nutshell, electrons have a shorter commute in 65-nanometer chips, so performance goes up. The gate length--the distance electrons travel to get from the source to the drain on a transistor and thereby flip the transistor on--drops from 50 nanometers to 35 nanometers in 65-nanometer chips.
    However, it was my understanding that power consumption will often go up with smaller geometries as leakage current increases with the smaller gaters. Can anyone elaborate on this?
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    1. Re:Reduce Power? by John+Courtland · · Score: 5, Interesting

      There's all sorts of problems when you get that small and fast. EMF interference, gate jumping, electron migration. The thing basically is a small radio transmitter, and starts causing itself problems just by running so fast. They need to really start designing more intelligently, unlike (as a previous poster stated) "ramping it up".

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    2. Re:Reduce Power? by batura · · Score: 3, Interesting

      While leakage is a big problem, its not as big as the power usage per switching transisitor, which if P = C * F * Vdd^2. This is the power consumption when the transistor goes from its high to low state and reducing the distance between gates reduces the capacitance in the wire. At really high frequency, you can make any wire seem like a capacitor, so its important to reduce the lenght of wire you're using.

  2. Sure, you can cram more circuits on a chip... by Not_Wiggins · · Score: 3, Interesting

    But, you'll also be incuring greated magnetic field interference. Heck, the thing will also generate more heat as driving current through smaller traces creates more "friction;" the chip might break itself simply under thermal load.

    Just because you can make it smaller, doesn't mean it'll function properly. There's a theoretical limit to how small traces can go before the interference makes signaling impossible.

    I can't wait to see how many processors get "down-binned" once they ramp up production with this tech. 8/

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  3. 65nm when 90nm isn't even out yet? hm by David+Jao · · Score: 4, Interesting
    Look, I am not a chip fabrication expert. I am merely a sideline observer. But based on my observations, Intel will probably not make it to 65nm in 2005.

    My position is based on nothing more than simple counting:

    • Intel achieved 250nm process technology (deschutes) in January 1998
    • ... 180nm (coppermine) in October 1999, although availability was scarce until January.
    • ... 130nm (northwood) in January 2002
    • ... 90nm (prescott) is not out yet, although it is supposed to be out in fourth quarter 2003. I'm going to go out on a limb here and predict January 2004.
    Their track record is clear: the average time between circuit size improvements is two years. Based on their history, 2005 would be a stretch, with the most likely release date falling somewhere in early 2006.