Intel To Produce 65-Nanometer Chips In 2005

Ridgelift writes "In keeping with Moore's Law, Intel will begin mass-producing chips using 65-nanometer process technology in 2005, according to a ZDNet article (additional coverage at EE Times and The Inquirer). Intel recently produced a Static Random Access Memory (SRAM) cell at 0.57 square microns, in comparison to 90-nanometer process measuring 1 square micron. "You can get a 40 to 50 percent increase in clock speed with no further improvements" says Intel director Mark Bohr."

Comments

Intel culture

[BiggerIsBetter]

What a beautifully telling Intel quote that is, "You can get a 40 to 50 percent increase in clock speed with no further improvements". Just keep ramping it up boys.

Bohr?

[Anonymous Coward]

Bohr? I wonder if he really knows where the manufacturing plans are or where they're going.

Reduce Power?

[brandido]

According to the article,

Reducing the size of the chip improves performance, reduces costs and can potentially cut energy consumption. In a nutshell, electrons have a shorter commute in 65-nanometer chips, so performance goes up. The gate length--the distance electrons travel to get from the source to the drain on a transistor and thereby flip the transistor on--drops from 50 nanometers to 35 nanometers in 65-nanometer chips.

However, it was my understanding that power consumption will often go up with smaller geometries as leakage current increases with the smaller gaters. Can anyone elaborate on this?

Re:Reduce Power?

[John Courtland]

There's all sorts of problems when you get that small and fast. EMF interference, gate jumping, electron migration. The thing basically is a small radio transmitter, and starts causing itself problems just by running so fast. They need to really start designing more intelligently, unlike (as a previous poster stated) "ramping it up".

Re:Reduce Power?

[addaon]

The relative importance of leakage increases at smaller geometries, but for all geometries on the near horizon, the increase isn't enough to outweigh the decrease in 'normal' (switching) power usage. This will probably change around 40 nm, but at 65 nm we're still making serious improvements.

Re:Reduce Power?

[batura]

While leakage is a big problem, its not as big as the power usage per switching transisitor, which if P = C * F * Vdd^2. This is the power consumption when the transistor goes from its high to low state and reducing the distance between gates reduces the capacitance in the wire. At really high frequency, you can make any wire seem like a capacitor, so its important to reduce the lenght of wire you're using.

Re:Reduce Power?

[mlyle]

Nah, it's actually the opposite of that.

Since electrons have less distance to travel, the resistance of the dielectric is less and less will leak. In extreme cases, for very small geometries, quantum tunnelling becomes an issue as electrons disappear on one side of the gate and appear on the other.

But as other posters said, leakage is currently still fairly insignificant compared to the huge WOOOSH of power that goes into the chip when things switch. Although leakage is becoming now more important for devices that sleep and stop their oscillator to reduce power-- passive power consumption, for the same process, is directly proportional to feature size, die size, and the square of the operating voltage.

Re:Reduce Power?

[rsmith-mac]

At this point, without some sort of additional chip technology(SOI, tri-gates, etc), it seems very likely that power consumption will definately stay even, if not go up entirely. Every new scale of technology is a bigger problem to make work, as the (known) laws of physics aren't moving with it, posing a very absolute barrier. Whereas 350nm, 250nm, and even 180nm went off without a hitch(with companies even manging to stick some Cu in there), 130nm was a big problem for AMD and TSMC(makers of Nvidia's GPU's prior to the IBM), and even Intel was having problems depending on who you ask.

Currently, 90nm is looking especially difficult, as Intel has had to push P4's based on the technology back twice from when they originally intended to release them, putting us currently at Q1 2004. That introduction isn't looking very pretty either, with the Prescott being dubbed the "100wt monster"; a new cooler design is nessisary in most cases for Prescott CPU's, along with the new BTX case standard(repositions the CPU for better cooling) for later on in the 90nm cycle, and all of this is for a chip that runs hotter than its 130nm counterpart(Prescott only adds another 512KB of L2 cache and SSE3, along with general core fixes; this shouldn't have resulted in a net gain against the overall power use unless the shrink didn't drop consumption significantly).

Either way, Intel is going to be able to pull off 65nm, but without the aid of other technologies, all they're going to end up with is a very hot chip that will have little chance at a major clockspeed ramp-up in its lifetime.

Re:Reduce Power?

[Hoser McMoose]

There are a number of things going on here, but a few important things to think of.

First off, with previous shrinking of the manufacturing process you could run the processor at a lower voltage. Most 500nm chips ran at 3.3V, 350nm chips ran at 2.8V, 250nm chips ran at 2.0V, 180nm chips ran at 1.75V and 130nm chips now run mostly at 1.55V. As you can see pretty quickly though, the difference in voltage isn't as much as it used to be, and with 90nm production, that difference is pretty much zero, most 90nm chips will probably run at about the same 1.55V of current (130nm) chips.

Second, the Prescott does add a bit more than just cache. Alongside the new SSE3 instructions, Intel is also making some fairly major changes to the P4 core, fixing some of the potential problem areas. I haven't heard 100% official confirmation, but apparently it adds a barrel shifter (should be very noticeable for D.net clients if they do) and fixes some of the scheduling issues with multiplications. These changes are going to result in extra transistors, and extra transistors means more power.

Also, the Prescott is supposed to improve hyperthreading. This is a good thing from a performance standpoint, it means that you'll get more of a performance boost from running two threads at once. The downside is that it means that the processor pipeline will be packed more fully, again increasing power consumption.

In short, there's lots to consider, no easy equation to get you the power consumption of the new chip.

Moore's Law

[worst_name_ever]

In keeping with Moore's Law

Well, more like "keeping Moore's Law a self-fulfilling prediction for yet another generation of processors". ;)

This is great news

[Timesprout]

The gate length--the distance electrons travel to get from the source to the drain on a transistor and thereby flip the transistor on--drops from 50 nanometers to 35 nanometers in 65-nanometer chips.

For all those lazy or out of condition electrons out there, they only have to travel 35 nanometers now to get some work done.

I have no doubt they can do it.....

[Selecter]

But it seems to me to be rather premature announcement, supposing these chips will be out when Intel says they will be. I think Intel is starting to feel the heat from quarters they didnt expect, like AMD and Apple via the good graces of IBM. Athlon 64 looks like a winner and so does the IBM made G5. IBM and AMD both have great looking roadmaps for the future.

This smells like a another smear piece by Intel to me, kinda like paper launching the P4 Emergency Edition on AMD's rollout day for the Athlon 64.

Boo. Hiss.

Re:I have no doubt they can do it.....

[Selecter]

I thinks it's premature to build a few test SDRAM cells and then magically announce they are going to build chips using that tech in possibly less than 1 year and 1 month. It's far more likely they will not meet that target, given the real hurdles of fully implementing that process to overcome. A few SDRAM cells does not a P5(6?) make.

Also, someone is not telling the truth.

"The 65-nanometer chips will not include the IBM-touted silicon-on-insulator technology, either. "We have not seen any significant performance advantages with SOI," Bohr said."

Well, who is it? IBM and AMD are going with it. Who's wrong, Intel or IBM/AMD? I'd like to know.

Re:I have no doubt they can do it.....

[Erich]

SOI has a much different design methodology. If you are Intel and have a really great design flow for non-SOI, it may not be as simple as "just go to SOI."

Also, for complete systems, SOI has a problem in that memory density tends to be much lower... so your caches have to be smaller if they are on-chip.

Re:I have no doubt they can do it.....

[Bored Huge Krill]

"a few SDRAM cells"? 4 million is more than a few. And they're SRAM cells, not SDRAM. Kind of stuff you need for cache. It does give a pretty good indication of how well along the process is.

BTW, this is apparently being done at the fab known as D1D in Hillsboro - this isn't a small scale research lab, it's a full size production fab. That it is being done there indicates it isn't as far away as you might think.

As for your comment about SOI, why does it need to be so black and white? It's always a judgement about the benefit versus cost, and it's always possible to get the same result more than one way. IBM made a strategic decision to go down the SOI path some time ago. Intel has gone down the strained silicon path. Each has its advantages and costs, and either camp could switch to the other if they saw an advantage in doing so. But given that they have made different choices, it's unlikely that one is "wrong" and the other is "right"

40 to 50 percent increase?

[Anonymous Coward]

"You can get a 40 to 50 percent increase in clock speed with no further improvements" says Intel director Mark Bohr."

Yeah, I get those "40 to 50 percent increase" emails all the time...I've been deleting them as fast as they come in.

Ohhhhhh...wait.... He said CLOCK, not COCK
nevermind :-)
TDz.

Terrific

[ActionPlant]

So does this mean, with 60nm tech, the die can be four times as large with an increase of 500% power? If we're moving from 90nm to 60nm, in the same die size that effectively puts us at a 30% efficiency increase. Times four (heck, just add more layers if you need more circuits!)...well, I'm hoping this means we see 20Ghz chips in time for Longhorn's launch. Watch it crash in 1/5 of the time!!

Damon,

Sure, you can cram more circuits on a chip...

[Not_Wiggins]

But, you'll also be incuring greated magnetic field interference. Heck, the thing will also generate more heat as driving current through smaller traces creates more "friction;" the chip might break itself simply under thermal load.

Just because you can make it smaller, doesn't mean it'll function properly. There's a theoretical limit to how small traces can go before the interference makes signaling impossible.

I can't wait to see how many processors get "down-binned" once they ramp up production with this tech. 8/

. . should have been 64 nanometers

[Anonymous Coward]

If they were really thinking ahead, they should have tried for 64 nanometers. Then, when the chip size halves every few years according to Moore's law, it can stay a whole number of nanometers for a few more years yet.

Moore's "Law"?

[nacturation]

I've always wondered why it's called Moore's Law. After all, it's not something which is mathematically provable. You'd figure computer scientists and systems engineers would be a bit more rigorous and call it Moore's Theorem, Moore's Axiom, or Moore's Postulate (I'm not sure what the best terminology is for this kind of conjecture). Granted, it has been approximately held, but there's no underlying reason why processor speed couldn't increase by an order of magnitude in a few months given the right implementation.

Re:Moore's "Law"?

[taradfong]

Similarly, "Murphy's Law" was supposed to be called "Murphy's Axiom" but something got screwed up.

Re:Moore's "Law"?

[Oscar_Wilde]

Yes, but as you well know anything that can go wrong woll.

Is that enough?

[nnnneedles]

50%, hmm.

doesn't Moore's law require 100% increase every 18 months? Yeah I know Moore's law isn't really about speed, but still.

Re:Is that enough?

[Hoser McMoose]

Originally Moore's law stated that transistor density would double every 12 months. That was fairly quickly changed to say that it would double every 18 months. The current "law" states that transistor density doubles about every 24 months.

Long story short, we haven't really been following Moore's law for a little while, though we do continue to double the amount of bits we can stuff onto a piece of silicon at a fairly rapid pace. Intel's plan to bring out 65nm chips before the end of 2005 continues this trend.

FWIW IBM is also looking to bring out 65nm chips by late 2005/early 2006, while AMD is hoping to get their 65nm fab process up and running in their new fab early in 2006. TSMC and UMC are likely to follow in mid-2006, though I haven't heard any official comments from either.

I believe it works like this:

[mbessey]

On an individual-gate basis, smaller gates use less power, since there's less capacitance at the gate to charge or discharge. Of course, smaller gates mean more components in a given area, which increases power consumption.

These two effects should just about cancel out, since gate capacitance increases with the square of the feature size, and the number of gates drops at the same rate.

Which leaves you with the other effects (including leakage), which are all worse with smaller gates. So, a maximum-size part will have a higher power consumption on a smaller process, but if you took an existing design (like a Pentium 4) and rebuilt it on a smaller process, you should get a lower power consumption (and smaller/cheaper die size).

-Mark

PC Toaster

[DigiShaman]

With a large enough heatsink, I could put a few slices of bread between the fins. Not only will this new CPU toast your data, but your breakfast too.

Re:PC Toaster

[jon787]

what is scarier, you thought of it, or somebody did it

Stupid people do stupid things. :-)

[MacFury]

I've always wondered why it's called Moore's Law.

It's called Moore's Law because the guy at CompUSA would get funny looks if he said Moore's Theorem. Often times you must dumb down your speech and use improper or vague terms to be understood.

Sad and true, a winning combination!

ZD editors on vacation

[mackman]

"Leakage, the unintentional dissipation of electricity, among other phenomena, can also inadvertently raise memory consumption." I would have to disagree, unless they're watching Johnny Mnemonic.

Cool, but...

[EverDense]

Wouldn't Moore's Law have failed by now without AMD competing for market share?

Re:Cool, but...

[moehoward]

No. Intel is always competing with itself. They want to make their products obsolete as soon as possible so that people upgrade.

Please mod parent back down, as I have made him look foolish.

Re:Cool, but...

[dustinmarc]

Wouldn't Moore's Law have failed by now without AMD competing for market share?

I don't think this is because of AMD. I would attribute it more to the fact the Gordon Moore, the creator of Moore's law is a co-founder of Intel and currently the chairman-of-the-board. It's probably more of Intel employees trying to not upset the boss by keeping up with what he obviously feels is the appropriate rate for number of transistors on a chip.

Not really.

[TCaM]

From all I have read the new AMD fab, like most any other will start out at a given process size, likely 90nm in this case, but will be ramped down so to speak. Do you really think they are buying near a billion dollars worth of equipment that isn't in any way upgradeable? Do you think Intel builds entirely new fabs for each new process and just takes the wrecking ball to the old ones?

Also given that intel still isn't shipping any quantity or anything at 90nm I take the 65nm claims with a grain* of salt.

*the process size of said grain may vary

Re:Ouch!

[WinterSolstice]

So?

The plant in Dresden will actually work, producing actual chips. This bit from Intel is just vapor at this point.

Besides, Intel will have to re-tool, debug, and market anyway. It's not like AMD will be any different.

-WS

Remember kiddies...

[MachineShedFred]

For the most part, clock speed != performance.

Yes it goes to a large part of it within the same processor family, but it doesn't scale at 1:1.

Translation:

[raehl]

"You can make a 80% to 100% price increase without any further improvements."

A virtual certainty

[Alomex]

The superconductor industry has detailed plans which are known set several years in advance.

If 65nm technology is possible, actual design specs have already been approved and work has already started on the design of a fab facility. So there is no speculation in the report.

Questions.

[Veramocor]

1. Approximately how many silicon atoms in a nanometer?

2. Whats the likely minimum amount of atoms that you need for a transister. Would switching materials effect that limit?

Given these two it should be easy to predict the smallest transitor size, and thus when moores law has to end.

Re:Questions.

[henrygb]

This 2001 paper suggests that about three silicon atoms fit into an nanometre and that they could space "bumps" at 38 nanometres. But that was a long time ago.

Useless metrics

[tttonyyy]

Hmm... I'm having trouble visualising 0.57 microns square. Lets see - even with these reduced cell sizes, you'd need 3600 square meters (half the size of a football pitch) of SRAM to have one bit per person on the world.

Assuming a constant 50W/sqr.mm, that'd be 180GW of heat. Someone find me a heatsink for that baby!

Re:Useless metrics

[Bender_]

Hmm... I'm having trouble visualising 0.57 microns square. Lets see - even with these reduced cell sizes, you'd need 3600 square meters (half the size of a football pitch) of SRAM to have one bit per person on the world.

Yes, I know its the fault of the metric system, everything would have been easier with mils, Angstrom and squarefeet.

But the correct result is 0.0036 m^2. Does a Gigabyte of Dram (=8 Billion Bits), which is obtainable in todays technology, take up a football pitch? no!

Haven't we been here before? .90 blues...

[Chordonblue]

Isn't that close to what they said about moving to .90? That, uh, didn't happen. The Prescott is coming in at over 100 watts - CASES will need to be redesigned to handle the heat output.

Intel bet their farm on being able to ramp up clock speed as opposed to making a more efficient chip (ala Opteron) and they're finding it harder to keep up. Take a look at the efficency of even a Pentium M at 1.3 GHz and you'll see why this is important - at least from a technical standpoint.

But I guess if you're whole marketing plan is based upon clock cycles, .65 *might* be important. All I know is .90 really didn't solve this problem for them to the extent .13 did over .18.

Re:thats all fine & dandy

[NWRefund]

Just because they say, "You can get a 40 to 50 percent increase in clock speed with no further improvements," doesn't mean they aren't going to implement further improvements anyway.

Does it say in that article that the new processor will be 32 bit x-86? No. It doesn't give any specifics at all, as a matter of fact.

Intel has a very talented marketing department. Whether or not you like them as a company, you at LEAST have to admit that. This is exactly as someone else has mentioned - it is a slap in the face to AMD who, try though they might, are still drowning in red ink.

Don't berate this new manufacturing process until you have a little more info on what they're going to make with it, hm?

65nm when 90nm isn't even out yet? hm

[David Jao]

Look, I am not a chip fabrication expert. I am merely a sideline observer. But based on my observations, Intel will probably not make it to 65nm in 2005.

My position is based on nothing more than simple counting:

• Intel achieved 250nm process technology (deschutes) in January 1998
• ... 180nm (coppermine) in October 1999, although availability was scarce until January.
• ... 130nm (northwood) in January 2002
• ... 90nm (prescott) is not out yet, although it is supposed to be out in fourth quarter 2003. I'm going to go out on a limb here and predict January 2004.

Their track record is clear: the average time between circuit size improvements is two years. Based on their history, 2005 would be a stretch, with the most likely release date falling somewhere in early 2006.

Ooops, for got to square properly

[FuzzyDaddy]

1 square meter = 1 meter*1 meter = (10^6 micron * 10^6 micron) = 10^12 square microns.

1 square meter is NOT 10^6 square microns.

But bonus points for being the first one to make this mistake in this thread, someone always does.

2005? Maybe the end of 05

[doormat]

Look at all the problems they are having with the 90nm process right now? That thing is leaking current like you wouldnt believe. Power dissapation is 90-100W. Heat is a big issue. I'm thinking something is going to have to happen to lower current bigtime. Remember thats 100W at 1.3V or so, for 77A, whereas the current P4's use 70W or so at 1.5V, for 47A.

Intel makes miracles happen

[jackstack]

I dunno how many people really appreciate how incredible the contributions that Intel has made.

I recently learned that thier 3GHz processors possess 1.2nm (12Angstroms) gate oxide thickness. I'm not exactly calibrated, but it can't be more than a Si atom conected to an Oxygen connected to a Si atom conected to an Oxygen along the thickness direction. And this is *consistently* done across a 300mm wafer (~1 foot!). It's just insane!

Guess what Intel, I don't want it

[BlueCoder]

I'm sure as hell not going to buy one. The heat issue makes me nervous, but electricity costs money. Am I going to have to call up an electriction to install a dedicated 240 volt circuit just to run a computer? I don't think so. I just don't need it that bad.

Do not make the cores any more complicated, just shrink them and run then at a lower voltage. Not put 8 to 16 cores spaced out in one package. Same power consumption, more computational power. And since you don't need to run the chips at higher voltage and frequencies, you get more yield for those extra cores.

And BTW, this is way too soon for 65 nm. I just don't believe it. Maybe by late 2006.

BTW, on your next chip set, please kill the floppy controller and just rely on the BIOS to use a USB floppy drive if someone really needs it. On my next system I'm not even going to bother putting a floppy drive in it and instead rely on flash memory. You might as well kill the serial, parallel, and PS/2 ports in the chipset and similarly rely on them connected through USB. If someone really needs the real deal then they can install a PCI card for such lagacy support. But be sure to include 1394 support just so USB isn't overly relied upon and there is an alternative.