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The Arrival of Very Small Memory
Roland Piquepaille writes "After the ages of DRAM and SRAM memories, is this time for nanotech memories? ExtremeTech says that "molecular memories" as well as memories based on carbon nanotubes are emerging. With these nanotech memories, several startup companies are envisioning future chips mixing logic, memory and reconfigurable computing elements. One of these promising startups is ZettaCore, which has built a prototype of a molecular memory designed to replace both SRAM and DRAM kinds of memories. These molecules, which are about 1 nanometer in size, are also self-assembling, meaning that they can be manufactured with existing equipment used in the semiconductor industry. This overview contains more details about the technology and includes a diagram of these molecules in a memory array."
64 bit computers can have up to 18Tb of RAM, but with motherboard physical limitationss it iss not possible. Even with 4Gb dimms (which are expensive) your lucky to get more than 16Gb out of standard motherboards. With this technology, We will be able to break this barrier, and do wonderful things in small spaces.. I for one, welcome my 18Tb Dimm!
I have a fetish for traffic cones
this seems to bee ideal, looks like it will need little power for keeping data in memory.. however it might be terribly slow or degrading in time, the article is kind of sloppy on the details of this. anyone?
I hope their research is better than their PR. Or maybe their technology really is unique!
I mean, if the chips become so much smaller, it's easy to see the capacity of i.e. Ram chips will reach levels unimaginable now.
But how are these bits gonna be addressed ? you need *lots* of pins, and how to connect those pins to the logical layer ?
I guess motherboards, processors and such need to be radically redesigned to be able to use this new technology.
How long would it take before mainstream mobo's use other (like i.e. photons instead of electrons) than conventional techniques ?
just curious
r.
I do agree with most of your points, however I don't think you should doubt consumer demand:).
I see every new program require more memory, more porcessing power. More and more information is processed by computer, which does require memory. Even if we could momentarily reduce or maintain memory needs through optimisation of the programs. In the end we will need better, faster and smaller memory. Wheter that is now or not I don't know but in the end the demande will be there.
Additionally, if this memory can be used in a persistent way, it would allow for high density, high reliability, and high speed data storage. Then It could really be the next big thing.
Whether you're a troll like the other guy says or not, there are thousands of companies that employ engineers to develop technology and then licence the technology to companies like motorola, intel, etc. The technology may require some degree of marketing to achieve critical mass usage, but that's irrelevent because if there's enough economic value (which this project practically guarantees, eventually) a larger company will either license it or develop its own.
Read jack phelps dot net
I could not grep any 'Bandwidth' occurence in the article.
What's the use of having a 4mm 18Tb chip if the bandwith still is 1Mb/s?
As they used to say: Never underestimate the bandwith of a truck full of tape drives
> OK, where are there existing semiconductor plants
> using nano-tech self-assembly techniques?
> That's an odd statement, implying the current UV
> light and mask etching equipment could just as
> easily do nano self-assembly.
First of all, "self-assembly" is not "nano-assembly", it is just chrystallization. The process is chemical in nature and would require similar equipment to that of circuit board etching. Second, mask etching is still required to draw the address wires on the silicone substrate. All they do is change the "bit" material, the rest will be pretty much the same as a regular memory chip.
You are assuming a bit addressable memory?
Actually, I know that you probably meant MB, but this is a significant point. If your 64bit computer had only word addressable memory (i.e., 64 bit chunks) then the same addressing could address 8 times as many bits (to the word level) as a byte addressable memory could address (to the byte level), and larger chunking is also possible. There could, e.g., be an alternate set of instructions that only addressed information to, e.g., to KB level, or to be more practical, to the 8MB (or 16MB) level (used for memory mapping LARGE disks).
The number of bits does, indeed, tell you how many separate addresses you have, but it doesn't tell you the interpretation of those addresses. There have been bit addressable machines. The CDC 6000/7000 series had 60 bit address chunking (for the main processors...I believe the peripheral processors had character [6-bit] addressability). And there have been many other choices. What the best choice is depends on a mix of what you intend to be doing, and what your hardware is.
So lets look forwards a few years. Unicode is likely to make 16-bit characters the most common chunking size, so byte addressibility will probably go by the wayside and be replaced by 16-bit chunking. This will probably quadruple the number of applications that can use "character-sized integers" as their integer of preference. So double-byte addressing will become the dominant form, and byte instructions will become deprecated, much as bit-level instructions have been deprecated. (They're still kept around for special purposes, but they're hard to reach from anything higher than assembler.)
Given that, byte size addressing will become unused. Probably IO between registers and RAM won't even deal with anything as small as a double-byte. 64 bit chunks are probably the minimum size that will be handled. (Makes the bus design simpler if you just drop any excess you aren't interested in.) And quite likely even that won't be the minimum size...depending on CPU register memory.
Remember, we're still in the early days of 64-bit CPU design. I may doubt that we'll ever go to 128-bit CPUs, but just consider the number of op-codes that even a 64 bit register allows. What I expect instead is that CPU chips will develop large on-chip RAM caches, supplemented by even larger L1-caches, etc. And that an on-chip SMP configuration will develop...how many processors? That will be determined by experimentation and evolution. But the limitation of the pin-outs at the edge of the chip will give a strong reason to find ways to handle compressed data forms. (Compressed here is more like the kind of compression that vector graphics gives over pixel graphics than like bzip2.) Say chips optimize out at 8 cpus per chip. The typical instruction for data from outside the chip would be "move a block of data from the L1 cache to register set n" or "Fill the L1 cache from RAM location x". Which means that memory addressibilty wouldn't be even at the 64-bit level, but at some higher level. Probably, say, 1/8th of an L1 cache. And the L1 cache would be addressible to a smaller level, say 4 64-bit registers. (N.B.: These are wild guesses, merely intended to indicate the kind of addressing that I see as plausible).
So how much memory could a 64-bit cpu address? O' at a wild guess, 2^64 * 64KB. Or more. Or less. (Sorry, it's a quite wild guess.) I don't know what prefix to use for that kind of RAM size, but TB isn't in it.
Of course, this isn't the first generation of 64-bit chips. But we're talking about a pretty speculative form of RAM here...so the CPU that uses it will probably be a generation or two more advanced than the current ones.
I think we've pushed this "anyone can grow up to be president" thing too far.