IBM Claims World's Smallest SRAM Memory Cell

nokiator writes "IBM issued a press release today claiming that it has built an SRAM memory cell that is ten times smaller than those currently available. My interpretation of the PRese in this release is that IBM will be able to build 256Mb or 512Mb SRAM chips or integrate 32MB or more SRAM into processor dies for cache applications in the future. Of course, showing some SRAM cell prototypes is a long ways from being able to manufacture this technology in a cost effective way. There is no information in this PR about the speed or power consumption of SRAM blocks that can be built with this new cell technology. This is not likely to be a potential DRAM replacement for mainstream applications as DRAM already offers more than ten times density compared to SRAM at much better cost."

Comments

Re:Chips = what?

[ottffssent]

The memory modules you put in your computer are composed of DRAM chips. DRAM uses a capacitor and a transistor per cell (plus sense amps, decoders, etc.). DRAM requires refresh (the charge on the cap leaks off) but is relatively low-power and very dense. SRAM uses no capacitors, but more transistors (4 or 6) per bit; it's higher-power but faster and doesn't require refresh.

So, SRAM density has nothing to do with DIMMs you put in a computer. It's used for on-chip caches (and off-chip caches), but is too expensive for main memory. Denser SRAM means that Opteron you've got with 1M L2 cache could have 4M or 8M if IBM can mass-produce the stuff.

DIMMs usually have 16 chips (18 for ECC modules). So, if you have 512Mbit DRAMs, you put 16 of them on a module and you get 8Gbit = 1Gbyte. Gigabit DRAMs can make 2GB DIMMs. 2Gbit DRAMs are needed to make 4GB DIMMs; they cost hundreds of dollars each (and you need 16!), which is why 4GB DIMMs are so amazingly expensive.

Re:Density vs Speed

[gazuga]

True -- SRAM has a much faster access time and is usually used in caches (such as on-die CPU L1 and L2 caches). However, since it is so much more expensive than DRAM, you don't see it used for system memory.

Re:IBM Rocks

[Martin Blank]

Their server division buys most if not all of its parts from other companies, excepting perhaps the PPC chips. Cases, CPUs, memory, video chips, and most likely even motherboards are manufactured by other companies, who probably also have a more direct hand in design than does IBM, which may only do oversight engineering such as reviewing final designs to ensure there are no significant bottlenecks or thermal build points.

I had better elaborate

[Sigurd_Fafnersbane]

The problem with E-beam is that it is a serial process. In effect you have to draw every single transistor using a megnetic field to move the electron beam.

What makes IC manufacturing in general manufacturable is the fact that you are using photo lithography with an optical mask through which you expose the wafer. This is a parallel process whereas E-beam, which can be good for engineering samples, sucks for manufacturability.

Re:I had better elaborate

[karvind]

For prototype demonstration, e-beam is acceptable. People in lithography know that they can ultimately print smaller (with expensive reflection optics and using F2 lamp source). That process development is done in parallel with device/circuit technology. In early 90s no one thought that they would be able to print 100nm lines with the type of tools they had. But still active research was done using ebeam to justify the need to made smaller devices. If smaller devices don't give performance benefit, there was no need for miniturization. This positive feedback triggered advancements in lithography. And E-beam is still used to make masks ($100,000+ spent for critical levels). This work is definitely worth mentioning. And it will be presented by David Fried at IEDM conference. I have priviledge to know Fried when he was a graduate student at Cornell University trying to make independent gate finfets. -a

Re:I had better elaborate

[Anonymous Coward]

The e-beam process was excruciatingly slow. In fact only a select few chips on the wafer were e-beam exposed. It has definately not scaled in speed like with other processing technologies. BTW, IBM only had 1 sram cell work in the end. Both of the wafers getting the processing underwent extensive rework. If the cell tests failed, they would strip several layers off and try to build it back up. Some of the processing was even done on tools from the 80's. I find it amazing they had the 1 cell work at all. But it felt pretty good in the end when it did work.

Re:These memory cells are so small...

[Anonymous Coward]

It's not the smallest, read this post.

SRAM can serve as a DRAM replacement

[Jailbrekr]

If you can shrink SRAM down to a size equivalent to DRAM, then it CAN serve as an effective replacement, and here is why:

1) No fancy control logic. DRAM needs to be refreshed on a regular basis. SRAM is a straight "chip select, read/write" type of ram.
2) low power. Because it is not being constantly refreshed, it can hold those bits with far less power. Thats why you see NVSRAM and don't see NVDRAM. Imagine having 1 gig of RAM that is battery backed up?
3) One can argue that without the control logic, it will be theoretically faster.

The OP is mistaken when they say that it will never serve as an effective replacement to DRAM. On the contrary, it will be an awesome repleacement.

Re:IBM Rocks

[curious.corn]

Bullshit... I once saw a low end intel IBM server... yeah... IBM is just like any other incorporated beige box assembler... Dell? Oh, you're so much wrong... listen: redundant monster fan, redundant power supply & cabling, redundant motherboard chipset, HotSwap PCI cards, HotSwap and (configurable) Redundant RAM (have you ever heard of RAM RAID? is that Redundant Array of Expensive Ram?)! You can pop the Bleedin' memory sticks from the machine Live! (I mean, the Dimm socket braces have leds identifying the faulty stick!)... drums roll... HOTSWAPPABLE BLOODY CPU BASKET (two at the same time... the thing waits brainless for the tech to drop the new one)! Yeah... just like that Dell... I'm daed shure this beast doesn't even let Winders touch the metal, there must be some virtualizing layer because I can't possibly believe Windows could ever survive in such an advanced machine without self-formatting in shame! Now boy, go blow your nose and play with your cold-cathode modded water-hyped P4EE...

Re:512MB cache?

[fitten]

Actually, it used to be based solely on the width of the general purpose registers in the CPU, implying that the CPU could process data in those sizes with one ALU operation (the ALU was as wide as the general purpose registers).

The 68000 you mention was considered a 32-bit CPU, or at least a 32/16 (32-bit internally, 16-bit data bus) as was the 68010 and it wasn't until the 68020 when it had a 32-bit data bus as well. There was even a variant that was the 68008 that was identically equivalent to the 68000 except it had an 8-bit external data bus. I have occassionally seen the 68000 referred to as a 16-bit processor, but the vast majority of times I've seen it discussed call it a 32-bit CPU.

As far as I remember, no processor has ever been 'named' relative to the address bus width. Even in the PC world I can't remember any time when the CPUs were 'named' relative to the address bus. Many 32-bit CPUs didn't have the full 32-bit address bus externally accessible. I can't think of any 64-bit CPU that has the full 64-bit address bus externally accessible.

As far as cache storage of data, the data formats are independent of the pointer size. The blanket statement that a 64-bit CPU effectivly 'halves the cache' is not true. If you have a program that deals only with pointers, then you'd have a point but 'int' on a 64-bit CPU is the same as 'int' on a 32-bit CPU (both being 4 bytes or 32-bits). It *is* true that a program compiled for 64-bit ISA will use *some* more cache, but that is entirely dependent upon the program itself. Again, a program that uses pointers a lot may use more cache than the same code on a 32-bit architecture, but a program that uses few pointers may not use much more (if any more) than the 32-bit counterpart, depending upon the datatypes used.

Re:Chips = what?

[curious.corn]

Nope, think a pendulum locked at the maximum swing position. Ok, I'm being cerebral so think a stat ram cell like two inverters interlocked so that the output of one forces the other in a state whose output forces the first one into the same state it was before like an oscillator that dosen't oscillate (it would if the second's output would force the first inverter to change state rather than maintain the current).

It's like a flipflop but wired differently. It's wicked fast because you don't have to refresh the ram pages and also reading isn't destructive (DRAM reading on the other had is because the charge in the MOS transistor has to be driven to the sense amp in order to measure it and decide whether it's a 0 or a 1). DRAMS are slow because you have to wait for the correct time slot while the chip isn't refreshing.

Re:50.000 at the end of a human hair

[SkinnyTurkey]

They say 50.000 at the end of a human hair. Do anybody know the actual size of this cell?

First match on Google for diameter of human hair is:
http://hypertextbook.com/facts/1999/BrianLey.shtml

Quote: "In my research, I have found the diameter of human hair to range from 17 to 181 [micrometer/microns]."

Assume a circular hair of 100 microns diameter, and assume the end of it is a flat circle of area Pi*Rad^2, or 7854 micron^2, divide this by 50000 and you get 0.157 micron^2 per SRAM cell.

The article mentions how IBM's SRAM cell is 10 times smaller than the current smallest. A Google for smallest SRAM cell gets you the Intel press release in March 2002 (too old?) that claims a 1 micron^2 SRAM cell.

Sounds about right to me. Given the range of hair diameter from 17 micron to 181 micron, the corresponding SRAM sizes would range from 0.0045 micron^2 to 0.51 micron^2. For exactly 0.1 micron^2 (a tenth of Intel's 2002 record), the hair diameter should be 80 micron.

Also, looks like the hair width varies too much from person to person to make it a realiable metric!

Re:Calm down, take a few valium...

[curious.corn]

You're right... I did get into a bumbling ram but it happens; I'm a bit burnt out!;-) Anyway, the rig I saw was (obvously) an IBM and I was enumerating, confusingly I agree, the specs that the tech had gloatingly told me while I was wiping the tears off my face when they assembled it;-) Now, the parent post was playing down IBM like "not much different from Dell" so I thought about that machine... ... ah, BTW, the machine itself was redundant... there were two of 'em... ("Oh my God, it's full of stars...")