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Strained Silicon to Perpetuate Moore's Law
An anonymous reader noted a story floating around about a new technology known as strained silicon (or maybe 'Stained' since the article calls it both ;) which AMD & IBM figure will make CPUs 24% faster. A little bit on how it works as well, but not much substance.
Is avaible from http://www.theregister.com/2004/12/13/ibm_strained _silicon/ and http://news.com.com/IBM%2C+AMD+claim+a+better+way+ to+strain+silicon/2100-1006_3-5487544.html?part=rs s&tag=5487544&subj=news.1006.5
Strained Si methods have been around for awhile. The PowerPC 970FX uses it, for example.
This method (called DSL, or "dual stress liner", not only stretches
the NFETs, it compresses the PFETs.
See a better article here.
Also, IBM is awesome.
The germanium is removed to help improve power consumption even further and lower core temps. This is where the IBM and Intel process differ. Intel does not remove the doping material from the wafers, and well... We see how that has affected their CPUs at 90 NM.
The new process only dopes the silicon under certain types of ICs and not others..
Actually Zdnet described it better so I'll just quote them
If anything this will finally allow for a G5 Powerbook and a
I hope you die painfully and alone.
It's strained silicon which gets it's name from stretching the silicon.
n edsilicon/
http://www.intel.com/labs/features/si12031.htm
http://www.research.ibm.com/resources/press/strai
Religion and science are both 90% crap..but that doesn't negate the other 10%.
The major Electronic Design Automation tool vendors today have yet to come up with effective ways on how to design with and verify very high gate densities devices on the digital side. If you think that 90nm is easy, ask Intel's Prescott core team on why they think 100W out of a processor is "normal". It's not just power, for example, but clock/power gating melding efficiently with the functional aspect of the design. Power analysis and signal integrity (i.e. crosstalk) design flows are only getting more and more complex, and more designs require respins to the tune of almost a million dollars per mask set.
Let's also not forget the analog world, since analog CMOS is notoriously difficult to design linearly across +/- 10% voltage ranges and through temperature and process variations. The problem was bad in 0.18um, very bad in 0.13um, awful now in 90nm and a nightmare in 65nm. All the secondary transistor effects that affect the usually "normal" operating points of logic gates only make things worse for the analog and mixed signal designers. This is not only for integrated analog and mixed signal interfaces but also for on-chip phase/delay lock loops and other assorted necessary goodies.
Nobody has the design expertise or the tools to effectively model all of these phenomena and get them working as efficiently as they'd like. In my experience, it's more of a hack and check mentality that is increasingly pervasive. Once you've stuffed so much analog and digital together, trying to functionally verify it to a particular degree of certainty is a major hassle. Data sets are getting astronomically larger, and simulations are still AFAIK not able to be multi-threaded, leaving you at the mercy of your computing power. Sure, you can use strained silicon and SOI to help you out, but you can't ignore the rest of the design issues because they will only get worse. This is where the EDA tool vendors like Cadence, Synopsys, Mentor Graphics and the rest of them need to come up with some more innovative ways of doing business. Otherwise, we'll have a lot of technology that is manufacturable but cannot be designed with.
It does after about 3.23 iterations...
24% does not perpetuate moores law.
Moore's Law has nothing to do with clock speed.
Not everything is analogous to cars. Car analogies rarely work.
Yes, it does. But, only for about four months. Given that transistor density is supposed to roughly double every 18 months...
0.24 x 18 months = 4 months and 10 days, or so
Those who complain about affect & effect on
Here.
Conventional processor speed it determined by the RC constants of its longest nets, not that much by the transistor speed. Your average FET can amplify signals in ~10 GHz range, and a bipolar -- GaAs, InP, SiGe -- transistor works just fine up to almost a 100 GHz, but it does NOT translate into digital processing clock speed much above 4 GHz, all due to wiring and its RC.
Paul B.
Replying to your sig:
Actually car analogies can work.
It's just that the wrong analogy is used. Clock speed is analogous to engine RPM. Further extending the analogy is IPC is equivalent to gear ratios. So my car at 3000 RPM may do 70 MPH in 5th gear, while a porche at 3000 RPM may do 125 MPH in the same gear due to the higher gear ratio.
Most people can understand that some chips can do more per cycle than others (IPC vs. gear ratio), and that a certain number of cycles (Mhz vs. RPM) is not an indicator of how fast you may be going/how much you get done.
You are correct in that Moore's Law has nothing to do with clock speed.
I am rather annoyed at the term "Moore's Law" in the first place however. It's not a law, theory, or hypothosis, it's an observation.
The laws of physics are not like traffic laws, they cannot be disobeyed. If it can be, then it is disqualified as a physical law, and it doesn't matter anyway.
one of the last episodes of Geeks in Space where this got mentioned as a submitted (but rejected) story? Looks like the submission approval process is taking a little long these days...
Think about 10,000% faster, or even more.
Strained silicon is just one of the last tweaks of the silicon era. The future is either carbon, or optics.
I'm not saying that 24% isn't good (it is). But rather that it's just a short-term achievement.
Strained Silicon is one of the three, relativly new, big processing technologies that makes chips go faster without changing any of their design. I say relativly new because, as someone mentioned before, they have allready been used on some PowerPC chips.
The two other main technologies are Copper wiring (used by intel since the coppermine PIII 800Mhz) and something called silicon on insulator or SOI. SOI is, to the best of my knowledge, only being used at IBM for the G5s but I could be wrong.
Instead of using silicon as the base material and then etching away at it, SOI starts with an insulating material (normally some form of Silicon like SiO2) and then layers the silicon on top with Silane gas etc.
Fast Federal Court and I.T.C. updates
... your numbers are the other way around!
;-)
In 1 ns (1GHz) light travels roughly a foot (1/3 of a meter) in air or low-Er coax. In 0.3 ns (3 GHz) it's 10 cm -- see, an order or magnitude!
But as I pointed out couple postings above and what teh GP I think had in mind was not speed-of-light limited communication latency, but RC delays of (non-matched) metal wires.
And it does not really matter how fast electrones move on the wire (though it matters inside transistor gate) -- you are limited either by speed of light propagation in matched line OR the time it takes to charge C through R to threshold voltage V.
Paul B.
actually, you want 18 months * log[2](1.24) i.e. how often a 24% increase has to happen for it to double every 18 months
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