Strained Silicon to Perpetuate Moore's Law

An anonymous reader noted a story floating around about a new technology known as strained silicon (or maybe 'Stained' since the article calls it both ;) which AMD & IBM figure will make CPUs 24% faster. A little bit on how it works as well, but not much substance.

Comments

More info...

[Folmer]

Is avaible from http://www.theregister.com/2004/12/13/ibm_strained _silicon/ and http://news.com.com/IBM%2C+AMD+claim+a+better+way+ to+strain+silicon/2100-1006_3-5487544.html?part=rs s&tag=5487544&subj=news.1006.5

not just Strained Si, but DSL

[tubbtubb]

Strained Si methods have been around for awhile. The PowerPC 970FX uses it, for example.
This method (called DSL, or "dual stress liner", not only stretches
the NFETs, it compresses the PFETs.
See a better article here.

Also, IBM is awesome.

IBM Does it again

[Erect Horsecock]

Strained silicon is not new tech, it's a couple of years old. The idea (at least the way IBM does it) the silicon wafer is "doped" with germanium which causes the lattice of the Si atoms to spread out further which allows carriers to travel faster across the transistor.
The germanium is removed to help improve power consumption even further and lower core temps. This is where the IBM and Intel process differ. Intel does not remove the doping material from the wafers, and well... We see how that has affected their CPUs at 90 NM.
The new process only dopes the silicon under certain types of ICs and not others..

Actually Zdnet described it better so I'll just quote them

In DSL, different straining materials are applied to the top of the transistor layer and then etched away from where they aren't needed or from where they can even degrade performance. Materials that create tensile strain to benefit N-channel transistors are applied across the surface of the wafer; chemical etching then removes those materials away from the P-channel transistors.

Subsequently, a layer of material for compressing the silicon lattice, which benefits the P-channel transistors, is applied and etched. The materials for straining N-channel or P-channel transistors can be applied in either order.

"On the P-channel transistors, you want to increase the density of atoms because the holes can move more quickly," said Nathan Brookwood, an analyst at Insight 64.

Kepler did not disclose the materials used but said they were fairly conventional nitride films and inexpensive. Plus, applying the straining materials after the transistor layer is complete is easier.

If anything this will finally allow for a G5 Powerbook and a

It's strained

[jayteedee]

It's strained silicon which gets it's name from stretching the silicon.

http://www.intel.com/labs/features/si12031.htm

http://www.research.ibm.com/resources/press/strain edsilicon/

The major problem is design tools, not technology

[StandardCell]

The major Electronic Design Automation tool vendors today have yet to come up with effective ways on how to design with and verify very high gate densities devices on the digital side. If you think that 90nm is easy, ask Intel's Prescott core team on why they think 100W out of a processor is "normal". It's not just power, for example, but clock/power gating melding efficiently with the functional aspect of the design. Power analysis and signal integrity (i.e. crosstalk) design flows are only getting more and more complex, and more designs require respins to the tune of almost a million dollars per mask set.

Let's also not forget the analog world, since analog CMOS is notoriously difficult to design linearly across +/- 10% voltage ranges and through temperature and process variations. The problem was bad in 0.18um, very bad in 0.13um, awful now in 90nm and a nightmare in 65nm. All the secondary transistor effects that affect the usually "normal" operating points of logic gates only make things worse for the analog and mixed signal designers. This is not only for integrated analog and mixed signal interfaces but also for on-chip phase/delay lock loops and other assorted necessary goodies.

Nobody has the design expertise or the tools to effectively model all of these phenomena and get them working as efficiently as they'd like. In my experience, it's more of a hack and check mentality that is increasingly pervasive. Once you've stuffed so much analog and digital together, trying to functionally verify it to a particular degree of certainty is a major hassle. Data sets are getting astronomically larger, and simulations are still AFAIK not able to be multi-threaded, leaving you at the mercy of your computing power. Sure, you can use strained silicon and SOI to help you out, but you can't ignore the rest of the design issues because they will only get worse. This is where the EDA tool vendors like Cadence, Synopsys, Mentor Graphics and the rest of them need to come up with some more innovative ways of doing business. Otherwise, we'll have a lot of technology that is manufacturable but cannot be designed with.

MOD PARENT UP!

[PaulBu]

Conventional processor speed it determined by the RC constants of its longest nets, not that much by the transistor speed. Your average FET can amplify signals in ~10 GHz range, and a bipolar -- GaAs, InP, SiGe -- transistor works just fine up to almost a 100 GHz, but it does NOT translate into digital processing clock speed much above 4 GHz, all due to wiring and its RC.

Paul B.