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Researchers Create 3-Dimensional Chips
Spy der Mann writes "Professor James Lu and other researchers of the Rensselaer Polytechnic Institute, managed to create three-dimensional chips (coral cache) to optimize the design of future processors and prevent overheating. "Make the interconnect wire shorter, and you cut the delay time," says Lu. "A simple way to make them shorter is to stack the transistors.""
Flat chips suck. These chips have flavor ridges(tm).
We complain about all the /. stories that are dupes but don't give proper credit to the editors when a non-dupe makes it past their radar.
Propz to Timothy for posting an original article! Keep up the good work!
Want to write a time travel game. Or maybe I already did.
Already been done.
I read in a paper recently where scientists have had some success in developing a four-dimensional transistor by using nanotubes to set up a quantum Klein bottle wherein the current passes through Bohr space and thus runs parahybolically.
In practice, you should actually be able to use this method to set up any n-dimensional transistor, provided you can find a sufficiently clean source of power. Modern power supplies have heretofore been plagued by an excess of static dissonance.
Essentially, they say this packs it denser. And a cube vs a flat processor = less surface/transistor. I see only factors which makes this *harder* to cool. Maybe someone can explain...
Kjella
Live today, because you never know what tomorrow brings
This is really cool stuff. Essentially they're making silicon wafers smaller by removing all the silicon in the substrate after the wafer is fabbed. Then they can put this few-micron-thick layer onto another fabbed wafer - perhaps made with a different process - then they can repeat the process. This allows sensor, analog, processor and memory to be made in the best processes for each function but with communication channels tens of thousands of wires wide and only microns long.
This article is worth reading - this is going to be huge. Also there is a really fantastic picture of a see-through microprocessor wafer with the article.
From the article:
Wafer-level stacking also allows for short connections between different types of chips. "Particularly today the industry is trying to combine memory with the processor, and more than half of the chip is taken up by memory," Lu explains. "When we stack layers, we have a processor on the bottom and layer the memory on top, with a short access time between them." Lu says the reduction of memory access time would be a huge advancement for large-scale computer clusters calculating nuclear reactions and weather broadcasting, for example.
"You are also creating new functionality," says Nalamasu. "Such technology has vast implications, for example, integrating biochips with silicon chips. The wonderful thing is that if we adopt this technology, we'll develop things we can't even envision today."
"Is life so dear, or peace so sweet, as to be purchased at the price of chains and slavery?" - Patrick Henry
There is, sort of. If the wires are shorter, they have less resistance end-to-end assuming they have the same thickness, are made from the same material, etc etc. Less resistance means less heat (and maybe core voltage could be lowered slightly too, since there would be less of a voltage drop). However, I honestly don't know how much heat comes from the actual junctions versus circuit pathways.
Please help metamoderate.
They do already do this... Intel chips have more than 7 layers on them. They arent really stacked wafers either; the film-growing, dopant implanting, CMP, and other processes can be repeated many times on the same wafer.
Didn't RTFA, but obviously this must be more than just the usual layering.
The current 7+ layer chips are talking about metalization layers. Wires, in other words. There is only one layer of transistors, which is at the top of the silicon substrate. I am not aware of any production process which has multiple layers of transistors.
People have been trying to build 3-D ICs for a long time because of the obvious benefits. The article describes a process of bonding multiple wafers in a stack, with wires going between the levels. Sounds to me like it would work, but it would only make the heat dissipation problem worse than it already is. My guess is 3-D chips will be used for low-power devices initially.
TTFN
"We've gone beyond zero insertion force -- you just throw the cubes into the enclosure and they will connect," said an Intel spokesman.
According to the spokesman, the functionality of the system will depend on the orientation of the chips as they land in their respective sockets. If the chips land on 7 or 11, Windows will run; 2, 3, or 12 produces the Blue Screen of Death. Similarly, any other number will produce an exception unless it is thrown again before a 7.
I'd like to thank the author, Spy der Mann, for having the foresight to make a coral cache of the site before posting. Kudos to you, mate.
It's all interrelated.
.
,Power can also be defined as :
The basic Power equation (in Watts) is Volts times Amps (V*I)
Aha! But from Ohms law, Volts is Amps times Resistance (V=I*R). And Amps is Voltage over resistance (I=V/R).
So substituting back into the original equation
P = (I*R)*I = I^2R
P = V*(V/R) = V^2R
So you can hopefully see from all that mess, any change of voltage,current,resistance will change power dissipated.
You are in a twisty maze of processor lines, all alike.
There is a lot of hype here.