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Intel Plans to Overhaul Chip Architecture
Carl Bialik from the WSJ writes "Intel is planning to announce an entirely new chip architecture later this month at the company's developer forum, the Wall Street Journal reports. The company isn't discussing details yet, but it's expected that Paul Otellini will discuss a 'technology foundation designed from scratch to improve energy efficiency and make it easier to add more than two processors.'"
One thing the article didn't make clear is what exactly Intel means by "A New Chip Architecture". i.e. Do they mean a new architecture as in the Itanic (but low power!), or a new chip architecture as in, "We're ditching the 20 stage pipeline in exchange for a more reasonable 6 stage pipeline, swapping out most of the control circuts for those from our StrongARM line, and rewriting the microcode to execute all of the Pentium instructions on a simple, low power RISC core."
While they could go either way, I hope they've learned from the Itanium and EM64T debacles that they should stick with a compatible microcode. Leave the super-instruction sets to the MIPS and SPARCs of the world.
Javascript + Nintendo DSi = DSiCade
Part of the roadmap Jobs was talking about?
Does this mean a new architecture like not being x86? Is this for Apple?
Conroe according to Anandtech...4 92
http://anandtech.com/cpuchipsets/showdoc.aspx?i=2
HJ
This is kinda funny in two ways..
'technology foundation designed from scratch to improve energy efficiency and make it easier to add more than two processors.'
Not overheard anywhere: "We are peeking through a knothole in AMD's fence and seeing what they are up to.
Nitpick: "The company isn't discussed details yet"
The proper word is ain't.
A feeling of having made the same mistake before: Deja Foobar
One has to wonder if Apple had any 'insight' to these plans when they signed the deal.
Perfecting Discordia
www.stevenvansickle.com
That just has to do with the market. In the start when the automobile was introduced, a person had to walk in front of it with a bell to warn for the danger. Since with computers there is still this risk, so a sysadmin has to run around and warn everybody of dangers in the use of computers, people just can not let go of the car analogy.
My wife's sketchblog Blob[p]: Gastrono-me
Well, Risk and Alpha are going away, and Itanium is the way of the future for HP-UX and OpenVMS. What was interesting was what they told us about the forthcoming Intel processors - the entire Alpha team was hired by Intel and the next gen intel chips will use the Alpha style switchless mesh architecture. This style architecture removes roadblocks inside the box -- no more intermediaries. Your data takes a straight line to its destination.
In other words - it connects processors directly to one another to render true linear scalability. This differs from other architectures in that there is no traditional bus, and you can add processors, memory and I/O capacity in a Lego block-like fashion.
They also mentioned they will be coming out with quad core in 2007.
I think it's entirely possible that this oblique announcement simply means that Intel is retiring Pentium 4 in favour of Pentium M derivatives. Intel's PR department probably feels that because they have been emphasizing the low-power aspects of the Pentium M, they need to downplay the fact that their new high performance architecture is simply yet another evolutionary version of a 10-year old architecture.
I'd say, if it works well and is competitive, does the age of the original design really matter? Keep in mind that the core if the Pentium M is heavily re-factored in terms of the overall logic design, improved branch prediction and so on. Making something completely new for its own sake isn't a worthy goal unless there are sufficient benefits versus the cost of such a design.
For all I know, the Athlon64 core might have as much similarity with the core of the Nexgen 5x86 chip as the Pentium M might have with the original Pentium Pro. AMD had trouble designing their own CPU core, so they bought Nexgen's know-how to do this, so there is at least a definite lineage.
It is pretty tough to do a clean-sheet re-implementation, I think a lot of times you might end up redoing the same work that was already done.
And the chips would be cool also...
exactly what I thought when I read the headline. The timing is too exact. It would have to be somewhat x86 compatable though you would think, else they wouldn't be developing on it now, they'd wait at least for prototype chips.
No... I doubt they'll be using the Pentium M core for this redesign. The new push will be for multithreading. The pipeline may shrink a bit, but long pipelines are nice because they allow for very high clock speeds due to low fanouts. When designing high power software going from 4 threads to 16 is often not too difficult. At least if you use the right paradigms. Combined with low-latency communication (L2 cache speeds) this makes for a very powerful combination.
.. . many of them don't need more power than what a simple 4GHz core can offer them. Those that require more computation than that will likely be reprogrammed to support multi-threading.
When designing such a machine its important to consider what the software will look like. Is it better to run 16 threads each with a CPI (cycles per instruction) of 1.2 or run 32 threads with a CPI of 1.6? This will actually push us much further back than the P3.
The cores on these processors are far more likely to resemble the original Pentiums. Simple pipelines, in-order execution, minimal instruction level parallelism. When the current P4 superscalar beasts can rarly pull a CPI of 1, whats the point of allowing 4 instructions to execute simultaneously (at least if the core is only executing one thread).
The new push will be to have 8 very simple cores (albeit with advanced SSE4 units with even wider vector instructions such as 256 or 512 bits) and allow each core to run 2 or 4 threads. This won't be hyperthreading as hyperthreading is a form of SMT (although Intel may reuse the name). It will be a form of fine-grained multithreading that allows context switches on L1 or L2 cache misses, as well as other latent operations. Of course their will also be logic to allow all the threads to run equally.
With these processors we'll be able to run 16-32 threads simultaneously (or almost simultaneously). For applications that can be massively threaded this will result in a huge boost in performance. For the single threaded applications that aren't easily parallelizable
This technology will scale tremendously. These new processors will essentially be supercomputers on a chip. I think this because of a presentation I saw by one of the lead P4 architects who was talking about future processors. This will be the future, and the time is now to rethink any applications you currently have and find someone competent in multithreading.
Phil
I'm told that AltiVec is vastly different (and superior) to SSE.
They're not very different at all, actually. Both are SIMD instruction sets essentially designed to achieve the same goals. That AltiVec is superior to SSE is true, but only if read literally. SSE2 is about an even match, with each having a few advantages over the other. SSE3 pretty much added all the horizontal data movement instructions previous incarnations lacked and is actually somewhat better than AltiVec.
If a job's not worth doing, it's not worth doing right.
Actually, I get fond memories when I think of old computers. If the Apple ][ and the Trash-80 didn't exist when I was waaay back in the first grade and doing stupid BASIC shit on them in school, I probably wouldn't have any interest in computers now.
Yep. Intel was very secretive about the Pentium-M's architecture when it first launched, mostly to hide the fact that it was based on the same P6 core as the old Pentium Pro (ie. something that's been around for more than ten years). The big announcement is a new x86 core, intended to replace the P6.
The other slightly embarrassing (for Intel) twist is that the new architecture will be a lot closer to the P6 than to the P7 ("Netburst") core used in the Pentium-4. Essentially, the Pentium-4 was a dead end, and all Intel's x86 plans now involve Pentium-M derived chips.
The main difference between the Pentium-M and the Pentium-5 (or whatever they call the new desktop chip) is that unlike AMD, Intel isn't putting 64-bit extensions in mobile processors. They claim that it's all about tradeoffs involving size and power consumption.
not quite actually. The big difference being that the cell architecture has a host processor, and many smaller sub processors. The subprocessors have a backwards memory model (which seems extremely confusing) in that each one has a scratchpad memory. Also each sub processor has a limited instruction set. What I described consists of many identical processors although the possibility exists for a chip to have one high-ILP core and many high throughput cores to optimize for both single and parallel app). However even with asymetric cores like that they'd all be capable of running any x86 instruction. Phil
Yeah, the idea behind Netburst was to streamline everything for clock frequencies as high as possible. This offered marketing advantages (before ppl became used to AMDs xx00+ ratings) and there was a time (shortly before and after the clawhammer) when it seemed like Intel had been right. It seemed that whatever AMD did Intel could just crank up the frequency another 200MHz, there was already speculation about 6GHz and more. But then they ran into the 4GHz barrier (and they weren't the only ones. IBM originally put the Cell at 4GHz+ and now they seem to have troubles at 3.2GHz) and since then Netburst has been dying a slow and painful death =)
Don't think of it as a flame---it's more like an argument that does 3d6 fire damage