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Nanotechnology Gets Finer
An anonymous reader writes "ZDNet reports on a new level of detail found in nanotech construction." From the article: "Japan's NEC Electronics has developed a technology to make advanced microchips with circuitry width of 55 nanometers, or billionths of a meter, the Nihon Keizai Shimbun business daily reported Sunday. Finer circuitry decreases the size of a chip and cuts per-unit production costs. It also helps chips process data faster."
We've had sub-micron CMOS processes for years now. Many of us are using computers with 90nm chips in them. But I've never heard of it called nanotech before. Maybe it's not inaccurate, but in my mind that term is more descriptive of other materials employing nanoscale materials that never did before (clothing comes to mind).
You don't use science to show that you're right, you use science to become right.
The hard limit is around 0.2 nanometers (the size of one atom in
a crystal structure - very roughly of course). The real limit is
that it gets more and more expensive to get closer and closer to
the hard limit, so don't expect anything below 10 nm any time
soon.
Oh, did I mention that you gain less and less from going smaller
because more signal is wasted as heat. Also, solid state physics
really changes around 30 nm (e.g. the concept of carrier mobility
loses meaning - you have to treat each impurity self consistently).
In short, going below even 30 nm is major money (compared with
the currently developed 35-50 nm processes, which are themself a lot
of money to put in production).
There actually is and it has nothing to do with math but physics. Obviously there is a limit when you start talking circuits that are made of single paths of atoms. Even before that there's a leakage that occurs leading to errors. There'd have to be a redundancy to overcome the occational lost electron so you get a deminishing return. There's talk of ways of avoiding the the issue but circuits a few atoms across are likely to be the limit. Anything beyond that will mean working on a sub atomic level and well beyond any known technology.
Bottom up construction has been a central tenet in some parts of the nanotechnology community. The idea that putting things together by controlling the position of individual atoms/molecules during fabrication will allow enormous breakthroughs in computing and other fields. But at least in the silicon based semiconductor business, the top down approach keeps marching mercilessly toward the bottom. This while bottom up synthesis/fabrication is still stuck at proof of concept. Might "top down" make it to the bottom - before the "bottom up" makes it to the top?
Intel has been building a 65nm fab and retooling existing fabs for 65nm. 35nm is planned but hasn't actually been done yet. It's unlikely to help much either, because current leakage at those levels is being insane. If you save 40% power by switching to a smaller manufacturing process and lose 35% back to leakage, that leaves you 5% better. With the costs involved in switching process sizes, you would have been better off not switching in the first place. Even past 90nm is getting pretty shaky in terms of leakage. Intel and AMD are both definitely goign to 65nm, but I don't know if there's much of a future for chips beyond that unless somebody comes up with some real ingenious tweak to the crystal structures.
We already have 65 nanometer process chips in production. Even this article, after parroting the NEC press release mentions that Intel is building a 45 nm process plant, which is a step further along than "NEC has developed a technology" to make 55 nm chips.
Here is an article from two years ago with an expected timetable for chip process width that exactly matches what we have seen since then: 90 nm in 2004, 65 nm in 2005-2006 and 45 nm in 2007-2008. There really isn't anything exciting about this press release from NEC.
For the record, that's 7 (seven) times as awesome as the Beatles themselves. Wow!
The hard lower limit is based on the sizes of the atoms involved, but you can't really get very close to a single atom thick without radically changing designs. For example, one of the thinner parts in a typical CMOS circuit is the gate oxide layer. In typical semiconductors, this is composed of silicon dioxide. The problem is that if that is made only a single atom thick, at a given spot you don't really have silicon dioxide anymore; you only have silicon or oxygen. With current designs, you need to maintain a layer that's thick enough to still be silicon dioxide -- i.e. molecule-sized, not atom-sized.
Realistically, even getting close to that is pretty difficult anyway. Even at the present time, the gate oxide layers are starting to cause problems -- the gate oxide layer is supposed to act as an insulator, so no direct current flows through it. In reality, a little direct current will inevitably "leak" through, but in the past it's been pretty small. In current designs, the gate oxide layer is getting thin enough that this leakage current is becoming a substantial part of the total power drawn by the part.
There are ways around that, such as using a different material. When you thin the oxide layer, the conductors connected to each side of it can be smaller, and still maintain the same capacitance. Another way to achieve the same objective is to use a material with a higher dielectric constant (traditionally abbreviated as "K").
Silicon dioxide is also used to insulate between other conductors on the chip as well. Here, you generally want to reduce the capacitance between the conductors though, because increased capacitance leads to increased cross-talk (the signal on one conductor creating noise in a conductor nearby).
Therefore, semiconductor materials people are working in both directions: low-K dielectrics for insulation, that maintain the same (or lower) capacitance between conductors with thinner insulation, as well as high-K dielectrics to allow thicker gate-oxide layers (reducing leakage) while maintaining the increased capacitance of a thinner layer. These, however, typically lead to substantially more difficult (read: costly) manufacturing. Of cousre, there are a lot of other possibilities as well, and each has its own strengths and weaknesses. For example, some designs use strained silicon -- actually "straining" the lattice of silicon molecules in the crystal formation so they're either closer together or further apart. Other designs change the basic wafer construction -- a traditional wafer is simply a layer of silicon. SOI is Silicon On Insulator -- a later of insulation, with a thin layer of silicon over the type. Again, creating the wafer this way costs some extra, but more importantly (at least to the designer) a transistor built this way has something of a memory effect -- the way it acts at any given time depends not only on the voltage applied right now, but also on its previous state. While this may be usable for embedded memory it can be a real PITA for everything else.
Anyway, I suspect the real limit will be mostly economic: a current fabrication facility costs a LOT of money -- around 1 1/2 billion US dollars (non-US residents feel free to assume I really meant 1 milliard Euro).
This expense has already lead to a couple of things: even large companies often can't afford to build a fab on their own anymore, so they often have to form/join some sort of consortium to build a modern fab. Another business model simply separates the companies into two halves: fabless design houses, and then a few companies that just fabricate designs for various others. For an obvious example, neither nVidia nor ATI does their own fabrication -- they design chips that are then built (along with a lot of other people's) by Taiwan Semiconductor Manufacturing Corporation (TSMC). Of course, TSMC ha
The universe is a figment of its own imagination.
35nm is planned but hasn't actually been done yet. It's unlikely to help much either, because current leakage at those levels is being insane.
Although we might not gain anything by going below 30-35nm gates, don't overlook the huge fallout rate of current photolithography (if you can still call it "photo" when dealing with "soft" x-rays as the light source).
If you can produce, at your extreme limit, a 65nm feature, then trying to produce exactly 65nm features leaves almost no room for error. If, however, you can produce down to 5nm features, then you can manage 35nm features with a huge margin of error.
Thus, your fallout rate drops from the current of over 50% (or so I've heard - I don't know the exact figure), to very nearly zero.
The practicality of clock speed increases and heat/energy reduction aside, better photolithography (or whatever manufacturing techniques we eventually move on to) means higher yields of better quality at the same size.
Also, consider the fact that some parts of a modern CPU run a LOT faster than other parts - Compare addition with division, for example. Addition has taken a single clock (less, actually, but assuming a serial dependancy, you can't do better than one op per clock) for several generations now, while division still brings the CPU to a crawl. If you could make a full adder "fast enough" at whatever size optimizes energy consumption (90nm seems pretty good at the moment; 65 might waste more than it saves), while chewing through power to perform a division in fewer clocks with 15nm gates - That would both improve performance and save power at the same time.