Nanotechnology Gets Finer

An anonymous reader writes "ZDNet reports on a new level of detail found in nanotech construction." From the article: "Japan's NEC Electronics has developed a technology to make advanced microchips with circuitry width of 55 nanometers, or billionths of a meter, the Nihon Keizai Shimbun business daily reported Sunday. Finer circuitry decreases the size of a chip and cuts per-unit production costs. It also helps chips process data faster."

Comments

how small is a nanometer?

[winkydink]

circuitry width of 55 nanometers, or billionths of a meter,

55 of them to be exact.

Brotught to you by the Department of Redundancy Department.

Re:how small is a nanometer?

[iluvcapra]

For an idea of scale, a ribosome is about 50 nanometers across (it does alot more work than a copper trace, though).

Re:how small is a nanometer?

[Rei]

Also brought to you by the Department of Redundancy Department:

"Nihon Keizai Shimbun business daily"

Nihon=Japan
Keizai=business
Shimbun=daily newspaper (lit. New-Ask/Hear)

Re:how small is a nanometer?

[NanoGator]

They're just clarifying a term. Considering some of the stupid jokes I've heard about my nickname, it's pretty clear not everybody knows what nano means. (or gator, for that matter.)

Re:how small is a nanometer?

[GroeFaZ]

I prefer an analogy I came up with for myself, being sick of all the "width of a hair" anal-ogies I so often read. Maybe it's just as useless, because in one or the other direction, you'll always have to face distances that are far from what is important in everyday life. Ok, here it goes:

The moon has a minimum distance to Earth of around 360.000 km.
The International Space Station has a minimum orbit to Earth of around 350 km.
The pillars of the Millau Viaduct are 340 meters tall.
If we take the minimum distance to the moon as our reference meter, then the ISS would orbit Earth at around 1 millimeter, the mentioned bridge would have pillars of slightly less than 1 micrometer, and finally a ruler of 35 centimeter length or (a little less than) the circumference of a compact disc would be 1 nanometer.

Re:how small is a nanometer?

[Anonymous Coward]

Thats some kinda spyware right?

Re:how small is a nanometer?

[c_forq]

I which I could moderate your moderation as funny.

Is there a limit?

[TimeSpeak]

I don't see why there needs to be.... but i'm no math genius.

Re:Is there a limit?

[Anonymous Coward]

It's not about maths, it's about physics.

Of course there is a limit to how small circuitry can get. I'm no physicist, either, but I can't see how circuitry could get any smaller than an atom's width.

Re:Is there a limit?

[Compuser]

The hard limit is around 0.2 nanometers (the size of one atom in
a crystal structure - very roughly of course). The real limit is
that it gets more and more expensive to get closer and closer to
the hard limit, so don't expect anything below 10 nm any time
soon.

Oh, did I mention that you gain less and less from going smaller
because more signal is wasted as heat. Also, solid state physics
really changes around 30 nm (e.g. the concept of carrier mobility
loses meaning - you have to treat each impurity self consistently).
In short, going below even 30 nm is major money (compared with
the currently developed 35-50 nm processes, which are themself a lot
of money to put in production).

Re:Is there a limit?

[Belseth]

Is there a limit?

There actually is and it has nothing to do with math but physics. Obviously there is a limit when you start talking circuits that are made of single paths of atoms. Even before that there's a leakage that occurs leading to errors. There'd have to be a redundancy to overcome the occational lost electron so you get a deminishing return. There's talk of ways of avoiding the the issue but circuits a few atoms across are likely to be the limit. Anything beyond that will mean working on a sub atomic level and well beyond any known technology.

Re:Is there a limit?

[Anonymous Coward]

For gate length. Sub-15nm gate oxides are already seeing quantized effects from single-atom layers.

It will be interesting to see if there is a break from CMOS to some substantially different integrated transistor process in the next 20 years, like there was from bipolar to CMOS in the late 80s. People seem excited about nanotubes, but I don't see how they'll play well with lithography, yet.

Re:Is there a limit?

[Jerry Coffin]

I don't see why there needs to be.... but i'm no math genius.

The hard lower limit is based on the sizes of the atoms involved, but you can't really get very close to a single atom thick without radically changing designs. For example, one of the thinner parts in a typical CMOS circuit is the gate oxide layer. In typical semiconductors, this is composed of silicon dioxide. The problem is that if that is made only a single atom thick, at a given spot you don't really have silicon dioxide anymore; you only have silicon or oxygen. With current designs, you need to maintain a layer that's thick enough to still be silicon dioxide -- i.e. molecule-sized, not atom-sized.

Realistically, even getting close to that is pretty difficult anyway. Even at the present time, the gate oxide layers are starting to cause problems -- the gate oxide layer is supposed to act as an insulator, so no direct current flows through it. In reality, a little direct current will inevitably "leak" through, but in the past it's been pretty small. In current designs, the gate oxide layer is getting thin enough that this leakage current is becoming a substantial part of the total power drawn by the part.

There are ways around that, such as using a different material. When you thin the oxide layer, the conductors connected to each side of it can be smaller, and still maintain the same capacitance. Another way to achieve the same objective is to use a material with a higher dielectric constant (traditionally abbreviated as "K").

Silicon dioxide is also used to insulate between other conductors on the chip as well. Here, you generally want to reduce the capacitance between the conductors though, because increased capacitance leads to increased cross-talk (the signal on one conductor creating noise in a conductor nearby).

Therefore, semiconductor materials people are working in both directions: low-K dielectrics for insulation, that maintain the same (or lower) capacitance between conductors with thinner insulation, as well as high-K dielectrics to allow thicker gate-oxide layers (reducing leakage) while maintaining the increased capacitance of a thinner layer. These, however, typically lead to substantially more difficult (read: costly) manufacturing. Of cousre, there are a lot of other possibilities as well, and each has its own strengths and weaknesses. For example, some designs use strained silicon -- actually "straining" the lattice of silicon molecules in the crystal formation so they're either closer together or further apart. Other designs change the basic wafer construction -- a traditional wafer is simply a layer of silicon. SOI is Silicon On Insulator -- a later of insulation, with a thin layer of silicon over the type. Again, creating the wafer this way costs some extra, but more importantly (at least to the designer) a transistor built this way has something of a memory effect -- the way it acts at any given time depends not only on the voltage applied right now, but also on its previous state. While this may be usable for embedded memory it can be a real PITA for everything else.

Anyway, I suspect the real limit will be mostly economic: a current fabrication facility costs a LOT of money -- around 1 1/2 billion US dollars (non-US residents feel free to assume I really meant 1 milliard Euro).

This expense has already lead to a couple of things: even large companies often can't afford to build a fab on their own anymore, so they often have to form/join some sort of consortium to build a modern fab. Another business model simply separates the companies into two halves: fabless design houses, and then a few companies that just fabricate designs for various others. For an obvious example, neither nVidia nor ATI does their own fabrication -- they design chips that are then built (along with a lot of other people's) by Taiwan Semiconductor Manufacturing Corporation (TSMC). Of course, TSMC ha

Re:Is there a limit?

[Hal_Porter]

I wish people would stop relying on non
standard and bloated PC features like
80 column displays. A hard carriage
return every 40 characters means that
your post be will viewable without
reflowing on an Atari 800XL.

Re:Is there a limit?

[Helvick]

Parent needs to be modded up more it is the most coherent comment on the topic posted so far. One minor nit pick - a 65nm\45nm fab costs about $3.5billion see here for the investment required for Intel's Fab 28 in Israel. That's an increase of $1.5 billion on the cost of the existing 90nm\65nm Intel Fab 24 in Ireland .

Re:Is there a limit?

[Compuser]

Sorry, no. I never plagiarize (sic). I simply follow the slashdot
submission box and whenever I come to the edge of the line I
automatically hit Enter. Having grown up with typewriters, it is
a natural reflex. You'll see that my posts aren't always formatted
to the box size, because my instincts aren't 100%.

Re:Is there a limit?

[igny]

It's not about maths, it's about physics.

Clearly, he is no rocket scientist either.

Re:Is there a limit?

[rbrander]

" It won't come to a screeching halt at any obvious point, but expect to see smaller improvements spread further apart."

Nearly 10 years back, before the word "blog" existed, I did a little web article called The End of Moore's Law - Thank God! that used the info in two excellent Scientific American articles which hypothesized a slow levelling off of the Moore's Law exponent around ... well, a year or two ago, actually, rather than a few years from now. But close enough.

The second Sci. Am. article stressed that it was an economic decision and drew parallels both to aviation (aircraft grew in size rapidly until the 747) and to trains (the biggest-ever locomotive was designed in the 50's)

In both cases, you wound up with the entire market being needed to pay the costs of the last generation of development. Presumably, the "Last Fab" will require a consortium of Intel, IBM, AMD, Motorola, etc - and make chips for all of them to pay off the $10 Billion construction cost.

Re:Is there a limit?

[InvalidError]

$15B would not be such a big deal for Intel... it already spends bilions in process research, spends many more building experimental fabs and production lines, it already has two working 65nm fabs with two others being upgraded from 90nm to 65nm during 2006 and many more at 90nm. With Intel's volume, a single 10nm fab may be insufficient for itself, I do not think they would share - at least not until they got a second or third one. Since unused 10nm fab capacity would be expensive, I would not be surprised to see a pattern of owning only as many fabs as necessary to meet sustained demand and outsource the rest - it makes no sense to spend $10B on a fab capable of producing a bilion chips per year when all that is needed is an extra 200M units per year.

Like you said though, most other IC firms have insufficient high-speed, high-density IC volumes to make building their own bleeding-edge fabs make economical sense, we have already seen this pattern with coop fabs (AMD/IBM/Motorola for the K7 debut while AMD was nearly bankrupt) and from the rise of fabs-for-hire like UMC and TSMC. When fabs become too expensive and high-capacity, foundry JVs and coops will become necessary - production lines have to run near full capacity 24/7 since it costs milions to stop and restart them.

I vaguely remember reading an article in a computer magazine nearly ten years ago where the writer pinned Moore Law's (transistor count doubles every 18 months) demise to be around 2010 and the practical limit at 10-15nm. So far, that prediction appears to be reasonably on-target.

Don't we already have 35nm processes?

[Anonymous Coward]

Um? Haven't we had 65nm and 35nm processors for a while? Is this just another Slashvertisement?

Re:Don't we already have 35nm processes?

[PsychicX]

Intel has been building a 65nm fab and retooling existing fabs for 65nm. 35nm is planned but hasn't actually been done yet. It's unlikely to help much either, because current leakage at those levels is being insane. If you save 40% power by switching to a smaller manufacturing process and lose 35% back to leakage, that leaves you 5% better. With the costs involved in switching process sizes, you would have been better off not switching in the first place. Even past 90nm is getting pretty shaky in terms of leakage. Intel and AMD are both definitely goign to 65nm, but I don't know if there's much of a future for chips beyond that unless somebody comes up with some real ingenious tweak to the crystal structures.

Re:Don't we already have 35nm processes?

[MSFanBoi2]

Actually Intel is already starting the move to 45nm right now and expects to have the first foundries online in 2nd half 2007.

Re:Don't we already have 35nm processes?

[TerranFury]

You're probably thinking 0.35 and 0.65 micron... and there are a thousand of those to a nanometer, so that'd be 350 and 650 nm, respectively.

Re:Don't we already have 35nm processes?

[freidog]

Samsung is currently manufactering flash memory in at least limited quantities (don't know if it's in full production yet) on a 50nm process.
To the best of my knoweledge that is smallest process in production, Intel and IBM are certainly producig 65nm chips that will be on the market in the next few months.

Re:Don't we already have 35nm processes?

[pla]

35nm is planned but hasn't actually been done yet. It's unlikely to help much either, because current leakage at those levels is being insane.

Although we might not gain anything by going below 30-35nm gates, don't overlook the huge fallout rate of current photolithography (if you can still call it "photo" when dealing with "soft" x-rays as the light source).

If you can produce, at your extreme limit, a 65nm feature, then trying to produce exactly 65nm features leaves almost no room for error. If, however, you can produce down to 5nm features, then you can manage 35nm features with a huge margin of error.

Thus, your fallout rate drops from the current of over 50% (or so I've heard - I don't know the exact figure), to very nearly zero.


The practicality of clock speed increases and heat/energy reduction aside, better photolithography (or whatever manufacturing techniques we eventually move on to) means higher yields of better quality at the same size.

Also, consider the fact that some parts of a modern CPU run a LOT faster than other parts - Compare addition with division, for example. Addition has taken a single clock (less, actually, but assuming a serial dependancy, you can't do better than one op per clock) for several generations now, while division still brings the CPU to a crawl. If you could make a full adder "fast enough" at whatever size optimizes energy consumption (90nm seems pretty good at the moment; 65 might waste more than it saves), while chewing through power to perform a division in fewer clocks with 15nm gates - That would both improve performance and save power at the same time.

Re:Don't we already have 35nm processes?

[akuma(x86)]

Why is everyone so worried about leakage?

You can dramatically reduce leakage by tweaking the process to give you a slightly slower process. It's not the end of the world folks. It's just at this point in time, it makes more sense to have the faster process and pay for it with leakage power. In the future that may or may not be true.

http://www.tgdaily.com/2005/09/20/new_intel_65_nm_ lithography_promises_reduced_leakage_for_small_dev ices

With billions of dollars at stake - it is unwise to underestimate the ingenuity of device physicists.

Nanotechnology?

[Leomania]

We've had sub-micron CMOS processes for years now. Many of us are using computers with 90nm chips in them. But I've never heard of it called nanotech before. Maybe it's not inaccurate, but in my mind that term is more descriptive of other materials employing nanoscale materials that never did before (clothing comes to mind).

Re:Nanotechnology?

[GroeFaZ]

The term has, over the last years, become something of a catch-all phrase for all things below 100 nm, also including fairly ordinary chemistry, unfortunately. Originally, the term was invented by Norio Taniguchi, but broadly popularized by Eric Drexler with the famous book "Engines of Creation" (available for free as in beer at http://www.foresight.org/EOC/index.html). "Engines" was over the top in some respects and often criticized, but even ardent opponents of Drexler's vision of nanotech like the recently deceased Richard Smalley admit they have been brought into nanotechnology by this very book. Back in the days of "Engines", nanotechnology was strictly confined to the not yet developed "mass-manufacturing of devices to atomic precision and specification".

Note that Drexler himself has presumably ceded the term to its current usage and has called Intel's 90nm chips "nanotechnology", although it bears no resemblence whatsoever to Engines-style nanotech. He prefers "zetatech" (mega, tera, peta, exa, zeta) nowadays because of the quantity of atoms involved, but I think it's rarely used. Molecular Manufacturing is the preferred term for what used to be Nanotechnology. Let's see how many more rearguard action Nanotechnology has yet to fight before it becomes reality at last.

Re:Nanotechnology?

[Doppler00]

I wouldn't consider this nanotechnology myself. I mean, it is still using the same lithography process they have been using for decades, just scaled down moreso. Nanotechnology should really be defined as the ability to shape things on the molecular level with precise detail. That is, can they build a single transistor using just component atoms? That's much more impressive than shining a light through a retical and getting your resulting chip (or however they do it, actually, it's still very impressive considering how many layers they produce and the accuracy involved).

with decreased size...

[Anonymous Coward]

... comes increased RF interference and possible heat concerns, with more electrons flowing through the same amount of area.

What we need is chips that work smarter, not harder.

Re:with decreased size...

[ichigo 2.0]

I want chips that work smarter and harder.

Re:with decreased size...

[slavemowgli]

RF interference has been a problem for a long while - I remember first reading about this when the Pentium-60 came out. An article back then mentioned that future processors would have frequencies in the FM radio range, and that this would be a huge problem for chip designers.

Of course, chip designers coped, like they had doubtlessly coped with problems like that before, and nothing happened. The same will probably be true here, too: sure, there'll be problems, but the chip manufacturers will sort them out. After all, that's their job, and they've been doing the same thing for decades.

I don't think that RF interference will turn out to be a huge problem now. It didn't back when the first Pentium came out, and it won't now, either.

At least at the other end of the nanotech world

[Ogemaniac]

the most commonly used definition is "1-100 nanometers", so anything since the 90nm generation would qualify. However, I am not sure what definition researchers using the top-down, engineering approach use. I am a chemist and approach the problem from the other direction (trying to assemble lots of .2 nanometer atoms into organized multi-nanometer stuctures).

Will "top down" beat "bottom up"?

[janneH]

Bottom up construction has been a central tenet in some parts of the nanotechnology community. The idea that putting things together by controlling the position of individual atoms/molecules during fabrication will allow enormous breakthroughs in computing and other fields. But at least in the silicon based semiconductor business, the top down approach keeps marching mercilessly toward the bottom. This while bottom up synthesis/fabrication is still stuck at proof of concept. Might "top down" make it to the bottom - before the "bottom up" makes it to the top?

Re:Will "top down" beat "bottom up"?

[GroeFaZ]

I think conventional silicon semiconductors might never see bottom-up fabrication, for a couple of reasons:
a) There is too much money invested in the traditional top-down process, and
b) the industry will not abandon a proven concept for at best marginal improvements in a dying technology. As we know, silicone is doomed to fail as keeper of Moore's Law, because you can only reduce features to so such and such dimensions before tunneling effects kick in, heat ablation becomes an insurmountable problem, and the statistics of impurity induction fails in practice. These limits are hard-coded in the laws of Physics as we understand them, and cannot easily, as of today, be engineered around, if at all.
c) Silicone and especially silicone in semiconductors (thus including statistical impurities of other elements) is not a rigid, defined atomic grid, which is pretty much a requirement for a bottom up fabrication. Bottom up directs every atom or molecule to a specific, well-known place where it then remains, which simply doesn't apply in a material that's almost a liquid, constantly rearranging its atomic structure, especially at temperatures of a working CPU.

Of course there are other materials that could be used as semiconductors, like diamond, which will make a far superior material in every respect. But as long as there is so much money in silicone and as long as diamond wafer fabrication remains in its infancy, silicone will be the way to go. But eventually, the semiconductor industry will have to make the jump to diamond or some other material, to maintain Moore's Law of transistor density.

Re:Will "top down" beat "bottom up"?

[fossa]

It's silicon. Silicone is a polymer. With a melting point of 1414 degC, I find it hard to believe you'll get much atomic rearrangement in silicon at 65 degC or whatever your operating temperature may be. The rule of thumb for ceramics is to sinter at about 2/3 the melting point (850 degC for Si) in order to get enough atomic movement to rearrange atoms on any reasonable timescale and densify the ceramic.

One of the key issues in reducing CMOS transistor size is the dieletric properties of the oxide layer. Decrease the size, and you must decrease thickness or increase dieletric constant of the oxide layer. SiO2 is the oxide of choice due the ease with which is is grown atop silicon. Layers thinner than one atomic layer are impossible, and layers thinner than 2-3 atomic layers may not have high integrity. Finding a suitable replacement has proven difficult. Different transistor designs may mitigate this somewhat, but not forever.

Yet another press release

[sidney]

We already have 65 nanometer process chips in production. Even this article, after parroting the NEC press release mentions that Intel is building a 45 nm process plant, which is a step further along than "NEC has developed a technology" to make 55 nm chips.

Here is an article from two years ago with an expected timetable for chip process width that exactly matches what we have seen since then: 90 nm in 2004, 65 nm in 2005-2006 and 45 nm in 2007-2008. There really isn't anything exciting about this press release from NEC.

Re:Yet another press release

[grungebox]

Here is an article from two years ago with an expected timetable for chip process width that exactly matches what we have seen since then: 90 nm in 2004, 65 nm in 2005-2006 and 45 nm in 2007-2008. There really isn't anything exciting about this press release from NEC.

The reason chip process widths exactly match those numbers is because those are specific targets set by an international semiconductor processing consortium. It is what the industry hopes to achieve by certain dates, not what they expect to just happen by certain dates. In other words, they didn't sit and think "Hmm...I guess the way things are going we'll hit 90nm in 2004. Ho hum." They thought, "Fuck, we'd better get our asses in gear to meet the 90nm goal in 2004." I think that effort is worth mentioning since it is not trivial to move to a different processing scale.

Nanites

[anexkahn]

so when are they going to get strong enough to take over the enterprise?

Fab 28

[wyldeone]

Along similar lines, intel has announced the opening of Fab 28 in Israel, which will be used for making processors at a 45nm scale.

Re:Fab 28

[buckyboy314]

For the record, that's 7 (seven) times as awesome as the Beatles themselves. Wow!

In other news

[contrapunctus]

Telescopes see farther, and batteries last longer.

Re:In other news

[The-Bus]

Telescopes see farther, and batteries last longer.

Unless you're an iPod owner.

*ducks*

From the artice: $3.5 billion for a 45nm factory?

[the_humeister]

I would have expected it to be more. But the, what do I know what these things cost? Anyone know how much the previous generation factories cost?

BS Article

[Jason1729]

Chip fab size has nothing to do with nanotech.

Re:This sort of things always worries me

[fourtyfive]

You watch WAYYYY too much television...

Re:This sort of things always worries me

[kkek]

The only problem with that is that almost every new technology could possible be used for "evil" purposes. Does that mean that we should never invent new technology? No. Being careful is one thing, but stopping scientific progress because of paranoia caused by a science fiction show is something different.

Moving to finer geometeries is not panning out

[gupg]

Moving to finer geometeries is not panning out in standard CMOS processes anymore. Currently, the Intels, AMDs, ATIs & Nvidias ship with 90nm chips. However, the transition from 130nm to 90nm has been slower than the transition from 180 to 130nm. There are several reasons for this, but primarily leakage power is becoming worse, getting good yield on 90 took the fabs years (longer than before), a lot of people got burnt when they moved too quickly from 180 to 130nm, the area savings on area & increase in performance is no longer that much moving from one process node to another ... and so on.

So, even though Intel et al are right now sampling with 65nm chips, since most ASIC companies still have to move to 90nm, I believe the move to finer geometeries will be even slower than before.

http://www.amazon.com/exec/obidos/redirect?tag=sum itgupta-20&path=tg/detail/-/1402078374/qid=1085677 524/sr=8-1/ref=sr_8_xs_ap_i1_xgl14/002-9004614-239 2044?v=glance&s=books&n=507846

Re:Moving to finer geometeries is not panning out

[Jerry Coffin]

Currently, the Intels, AMDs, ATIs & Nvidias ship with 90nm chips.

At least the last time I noticed, nVidia was still using 110 nm. ATI's latest X1 series (R520-based) use 90 nm fabrication, but I'm not aware of these being available as real products yet. The previous generation (e.g. X800) were 110 nm, unless memory serves me poorly.

TI and IBM also produce 90 nm chips. IBM (same page as above) claims to have a 65 nm ASIC production capability on line as well, though I don't know whether they have any real customers for it.

--
The universe is a figment of its own imagination.

Re:Moving to finer geometeries is not panning out

[akuma(x86)]

Slower for TSMC or UMC. Intel has no problem with yields at 65nm. Intel is after all going to launch dual core 65nm NOTEBOOK chips early next year.

Intel is also laying down 3.5 billion dollars for a Fab in Israel which will be 45nm for 2007 production. Moore's law continues to have legs. It is ASTONISHING that this is something we take for granted! And in 2009, I predict 32nm. And in 2011, I predict 22nm. Guess where we'll be in 2013?

the area savings on area & increase in performance is no longer that much moving from one process node to another

Explain that to NVIDIA or ATI, where performance scales directly with the number of floating point units and hence is directly proportional to area.

The problem with designing for smaller geometries is that the ASIC tools aren't mature enough in time for the new process. Design rules increase geometrically as the process shrinks. Intel and AMD have in-house custom tools that deal with these problems since there is a very tight relationship with the Fab. TSMC and the like are more de-coupled from companies like Cadence or Synopsys.

To quote good old Jerry Sanders - "Real men have fabs"

How does new technology cut production costs?

[bmvaughn]

Wouldn't a finer, more intricate process RAISE the production cost? Poster needs to go back to college and re-take Common Sense 101.

Re:How does new technology cut production costs?

[NanoGator]

"Wouldn't a finer, more intricate process RAISE the production cost?"

Initially. But then the chips get smaller, more can be made at a time, and costs go down.

Re:How does new technology cut production costs?

[TERdON]

It sure does raise cost, exactly as you say. But if you're making the components smaller, you'll be able to make the chips smaller, implying:

1) more chips in each wafer
2) assuming same density of defects in the silicon crystal, a higher yield rate, as there is a lower chance that there is an error in each chip, as the area of each chip gets smaller. (easy demonstration: take a paper, draw 10 random dots on it. If you then split the paper in 8 pieces the chance of having a dot on a specific piece of paper is bigger than if you split the paper in 16 pieces)

1) and 2) together means that even if your costs will rise, as long as your density of errors rises dramatically (it isn't supposed to), you'll be able to get a lot more chips per wafer.

Conclusion: Even if the costs per wafer rise, as long as the cost per chip sinks, it will be profitable business.

Re:How does new technology cut production costs?

[anzev]

True. But you still have to take into account that the market gets saturated. Even though the chips are small I don't think they'll fit in an overcrowded market :-). Sorry, had to be sarcastic. Anywho, this already happened at the mobile phone market, so now its all getting service-orientated.

So, my point is, that it does raise the production cost which decreases significantly over time, but also increases the risk of overcrowding the market by lowering the cost. So it's a vicious circle and re-taking a common sense 101 class ain't gonna do you no good. If you want to learn how it's done, look at monopolies (M$ etc.)

Re:This sort of things always worries me

[NanoGator]

"Shouldn't we stop for a second and consider the negative impact this sort of things could have on our world?"

If we did that, then virtually nothing would come to being. You can stop new technologies from being developed, but you can't stop people from doing horrible things. The best you can do is broaden your abilities to deal with disasters when they happen. I hate to go all Godwinian here, but the same technology that destroyed the World Trade Center has also been used to revolutionize the world for the better. Whaddya supposed do?

Re:This sort of things always worries me

[Teun]

Lead Butthead

Hmm, there must has been a general concensus when your teachers gave you this name...

Plenty of Room at the Bottom

[Doc Ruby]

Nanochem promises to allow even tinier feature sizes. The atoms in a molecule are about half a nanometer across, but they can form structures with gaps even smaller. Benzene rings have diameters also about 0.5nm, and can be made in regular arrays as nanotubes. More complex structures can twist these feature spaces even closer, and in vast numbers of regular arrangement. Their production through chemical, rather than mechanical, engineering promises more efficiency, lower cost, and larger production yields.

We are now looking at the nanometer from above, pulling our micrometer structures towards the new horizon. Once across it, we will still use nanometer-scale engineering to produce picometer (and smaller) scale results.

Re:Plenty of Room at the Bottom

[grungebox]

Nanotubes have a very tough road before used in electronics, for several reasons.
1) Producing nanotubes of consistent chirality has proved very very difficult. Chirality is how "twisted" the nanotube is (chemists, I know that's a poor description), and depending on the nature of the chirality the nanotube can be semiconducting or metallic to different degrees. If you produce a huge amount of nanotubes but not all are semiconducting, or they're semiconducting but with different electronic properties because they aren't the exact same chirality, you have a humongous probem.
2) Producing long tubes has also been a major problem, although this one has made a lot more progress than the consistent chirality probem.
3) Difficulties with integrating nanotubes into solution processing mechanisms. Using nanotubes with silicon would inevitably cause a clash in fundamental production schemes (between "top-down" and "bottom-up") that can not be resolved in an economically desirable manner.

Unfortunately, lots of people think of computing as the jetliner industry. Jetliner speeds kept increasing for a long time, but they've plateaued because the costs and other factors (like sonic booms) of producing faster jets made them economically disadvantageous. So that's why commercial jets today are just as fast as they were in 1974. Same thing could happen to computers. I hope not, but it's an interesting comparison.

Re:Plenty of Room at the Bottom

[Doc Ruby]

One approach to nanotube quality control is to make them cheap and dirty, then separate them chemically or mechanically (centrifuge, phoresis etc). Especially with different electromagnetic properties by which to separate them. Doping nanotubes for different chirality, especially heterogenous chirality in a single tube surface, is one of the more compelling avenues for nanocomputing research. Tubes a few dozen nanometers in diameter and dozens of centimeters long (10K:1 ratio), which is a pretty long wire. Solution processing is yielding plenty of results for nanotubes, and the "fundamental production" problems you predict don't even prohibit Si/DNA coupling techniques (another nanotechnique).

I don't know why you're so pessimistic. Even if those avenues were hitting real obstacles, or faced implicit physical contradictions, the field is extremely young. Especially in shrinking engineering, even small gains create new tools which enable breakthroughs. The actual limits to microengineering we now face, heat dissipation, parallelization, silicon featuresize and others, are the reason nanoengineering is seeing so much investment. We are already seeing nanoRAM announcements even here on Slashdot, and even today we saw buckyball films announced for PEM-type electronics. I see no "sound barrier" for nanotech yet - to the contrary, I see nanotech slipping past the micro "barrier" ever more quickly.

Re:Plenty of Room at the Bottom

[trolleywobbles]

Yes, but a nanometer is a unit of spatial measurement that is 10-9 meter, or one billionth of a meter, so we can't rush this. While commercial products are starting to come to market, some of the major applications for nanotechnology are five to ten years out. Private investors look for shorter-term returns on investment, more in the range of one to three years.

Re:This sort of things always worries me

[IntergalacticWalrus]

"I hate to go all Godwinian here, but the same technology that destroyed the World Trade Center has also been used to revolutionize the world for the better."

Come on now, exacto knives are great but they never were revolutionary.

Picotechnology

[this great guy]

Nanotechnology Gets Finer

Frow now on, picotechnology it is.
Or reallyreallysmalltechnology.
You choose.

Re:Picotechnology

[IInventedTheInternet]

how about "/.'ersChanceOfGettingLaidTechnology"

maybe we'll be there in a couple decades...

Small size = boring electronics

[TerranFury]

It used to be, back in the 90s, that you could do all kinds of cool stuff: Dynamic logic, they called it -- precharge-evaluate, domino logic, zipper logic... google 'em; they're cool. Nowadays, we can't even do that. I was talking to a guy from AMD the other day; he explained that the leakage currents and noise levels are so high that everying ends up needing to be boring old AOI CMOS. "It's not as fun for the circuit designers as it used to be," he said. Ah well.

Quantum dots!

What's the drive?

[Mr2cents]

I was just thinking, what drives this evolution? Is it science-driven, or technology-driven? In other words, are there any scientific bariers left to take when reducing the size?

Re:What's the drive?

[berbo]

..what drives this evolution?

Its Intelligent Design!

and...

[Outsomniac]

LEON's GETTING LAERGERRRR

Re:This sort of things always worries me

[grungebox]

Shouldn't we stop for a second and consider the negative impact this sort of things could have on our world?

I heard that Ug-ug said that to Gok-nok when they were co-discovered fire.

Re:This sort of things always worries me

[NittanyTuring]

We most certainly do have to consider the potential negative impact of nanotechnology. If you don't believe Lead Butthead, maybe you'll listen to Bill Joy, author of BSD and co-founder of Sun Microsystems. In 2000, he published a fascinating article on the potential dangers of 21st century technology, nanotechnology included.

Some old book

[Illender]

Does anybody remember an old sci-fi book that talks about how the Chinese and the Japanese created miniature armies, and tried to take over the world?

hmmm..

Re:Some old book

[GroeFaZ]

Yeah I remember that one. Wasn't one of the Japanes divisions called "23rd Tamagotchi Division", nicknamed "Devil Spawns of Infernal Evil" (translation) or somesuch? Also, who could forget the dreaded "Pokemon Legion". More recently, the "Hello Kitty" spec-ops have joined the fight as well. The race isn't going too well for the Chinese, eh?

Re:From the artice: $3.5 billion for a 45nm factor

[Jerry Coffin]

I would have expected it to be more. But the, what do I know what these things cost? Anyone know how much the previous generation factories cost?

It's been in the billion+ range for quite a while. It depends not only on geometry, but also on capacity. Based on the price (and owner) I'd guess this is quite a large, high-capacity fab. Then again, 300 mm wafers translate almost directly to fairly high capacity, and I doubt anybody's building equipment for 45 nm to work with smaller wafers.

--
The universe is a figment of its own imagination.

Prior art

[SteveAyre]

So we're still 5 nanometers from something everyone has been doing for millenia...

Re:Where's the Nanotech?

[cnerd2025]

Please, do not say such things. Nanotech does exist and I have seen it with my own eyes (aided by an electron microscope, mind you). In fact, corporations are developing technologies and some have already developed technologies integrating nanotechnologies. New tennis raquets use nanotubes to become stiffer and stronger than the older models. Samsung has developed a display utilizing nanotubes which hasn't hit the market yet, but will once some issues are resolved (the display works fine, but it is a wee bit fragile as of yet). Also, right now it takes an incredibly long time to grow the nanotubes. The record for the longest nanotube is about 3 cm, and it was grown in about 2 days. The technology is truly fascinating. I recently attended a conference at GA Tech, and one of the seminars was about nanotech. Really a fascinating subject area. Nanotech is not synonymous with nanomachines; it is the engineering of objects on the nano scale (10^(-6) m). Though many companies use "nanotechnology" as somewhat of a buzzword, avoid saying that "no one" is investigating it or that "no one" has made anything with it. Ad hominem argument is a fallacy.

Comment removed

[account_deleted]

Comment removed based on user account deletion

Re:newspaper in japanese

[FSWKU]

***Extreme Offtopic Reply Warning***

It is. However, there are a lot of instances where the "n" sound (the only sound in the language not accompanied by a vowel, as opposed to others such as "na", "ni", "nu", "ne", and "no") is pronounced more like "m." For example, "shinjiru" (to believe/trust) often sounds more like "shimjiru."

Same case with "shinbun." Technically, they spelled it wrong in the summary, but it could be explained by saying they simply romanized the spelling. A similar parallele would be something like "Watashi no namae wa Takashi desu" where the "wa" is written as "ha," but most people who don't study the language are confused by the difference.

adapted to quantum Re:Is there a limit?

[hackwrench]

I wonder though, if the same processes can't be adapted to components with quantum effects.

Slapstick

[dimfeld]

You may be referring to Slapstick by Kurt Vonnegut, part of which described the Chinese breeding themselves over many generations to be smaller. The intent was that they could reduce their food needs, but they accidently went too far and became microscopic. Then any normal-sized person who breathed in a bunch of Chinese people would die when they clogged up his lungs.

Re:Slapstick

[Illender]

YES, thank you..
come to think of it, I may be mixing the memory of that book with, ummm, Isaac Asimov's Fantastic Voyage I think.., wasn't there a race for miniturization in that book?
But definitely Vonnegut.

Re:Slapstick

[dimfeld]

Not that I remember. I'm pretty sure the miniaturization thing was entirely an accident. But I read the book around 7 years ago, so my memory might not be entirely accurate.

Lots of room but little control

[Ogemaniac]

Sure, we chemists can make all sorts of little tubes, balls, rods, pyramids, etc. Unfortunately, as you said, they are usually a mixture of many different sizes (and hence properties) as well as contaminated with all sorts of crap. The SEM and TEM pictures you see in the journals are assuredly the prettiest of the bunch.

Worse yet, we have almost no control over the arrangement of our little tinker-toys. At best, we can get them to sort-of line up or form some sort of regular lattice on a large scale, or using something like AFM manipulate one at a time in order to study it (of course, this is infeasible on a production scale). We are a long way from being able to arrange these parts on a mass scale in any sort of arbitrary, complicated geometry.

Re:newspaper in japanese

[Ogemaniac]

I have never noticed "n" sounding like an "m" before "j" before, only before "b" and "p". This is for the obvious reason that m/b/p are formed by almost exactly the same lip movement. Very much like in English, where "kicked" ends with a "t" sound, not a "d" sound, but "feared" does wnd with a "d".

I'll have to ask my gf to say "shinjiru" a few times to see if I can hear what you are saying.

Evolution, Progress or Technology

[lloy0076]

Not to start a debate, but let's say that The Utopians develop nanotechnology that eventually allows them to survive the change of climate from what we have now to significantly warmer. Most of the other humans (and species) die...

Is this:

  * evolution?
  * progress?
  * some kind of perverted Intelligent Design where the intelligent designers were human?

Let's say that The Utopians develop nanotechnology that eradicates, say, the Dog 'Flu (which is as effective as Ebola Zaire and contagious by air).

How do we control who gets to have these nanotechnology units installed, with the following assumptions:

  * they're EASY to produce
  * they're INEXPENSIVE even by the billions to produce ...in other words there's no economic or technical reason why the whole world couldn't be "immunised" against Dog 'Flu excepting political ones?

Intriguing; I really don't believe that the size of nanotechnology robots is the issue - the crunch is the ethics.

DSL

Re:This sort of things always worries me

[Hal_Porter]

People that write articles like that will be first up against the wall when the machines take over.

You're better off saying there's no danger upto point that robot M1A1s start mowing people down, and then pulling a quick Baltar.

Besides, everyone knows that AI is impossible.

caos

[lop367]

ummm how small can it get?.... do our pocket will be also smaller.... knowing all what is up to come, dual core... quad core??... meaning BIG HEAD SINK

Picometer or smaller???

[Anonymous Coward]

Picometer or smaller???

Atom-atom spacing is on the order of angstroms (.1 nm). 100 picometers is an angstrom. In other words, with the current chemistry we can do today, we _are_ at the bottom.

The interesting goal we now face is not getting smaller, but getting bigger-- being able to exert order on larger and larger scales in interesting ways, i.e. self-assembly of these units into larger, more complicated devices.

Re:Picometer or smaller???

[Doc Ruby]

Let's say you make a lattice of 1Å (100pm) atoms with bond lengths of 1Å. The 3D geometry of the lattice can bring the atoms into proximity limit by their electrical repulsion and the angles of their bonds. That proximity can be shorter than their bond length - it can be nearly any size or shape. This is how enzymes make active sites with feature details at highly precise scales. Another analogous example, especially at these scales, is how relatively large wavelengths can combine to create differential beat frequencies at relatively much smaller scales. When we make devices out of intervals and gaps, we can get asymptotically small. This is, of course, how we already reach those nanoscales from our mesoscale starting engineering.

What's interesting about these kinds of small features, and chemical processes for their assembly is that they make not only smaller features, but also many more of them simultaneously. So nanocrystalline chemistry offers solutions (pun intended :) to both scaling resolutions smaller and aggregates bigger.

There is no bottom - hence Richard Feynman's famous lecture title, which I stole with pride :).

Re:Picometer or smaller???

[Doc Ruby]

The feature size is the operational size, with the characteristics that come from small sizes: speed, efficiency, sensitivity, multiplicity. The part as a whole can be much larger than the feature size. So even the 45nm feature size of the devices we're discussing in this thread are composed of much larger parts. The gaps are in fact the part of the device that matters, especially in micro (or nano) electronics, where "electron holes" are part of the essential mechanism. The question is how small can we make the operative portion of the device, because that's where the gains come from. The size of the enzyme is as relevant as the size of the die in a microprocessor: not very. What's relevant is the precision of the geometric distribution of the material, even if accuracy is statistical, in electronics (or photonics) or enzymes. The chemical processes don't necessarily scale up more easily with smaller features per se, but smaller features at nano or pico scale are manipulable by us today only with chemistry, which then offers better scalability than mechanical processes like laser etching or just plain photolithograpy.

Enzymes and DNA are natural nanotech (and smaller). They're good examples of using arbitrarily narrow spaces between larger building blocks as precision devices, especially in controlling information. And their efficiency also comes with inherently parallel production methods, leading to better parallelism in their useful operation. So I say that mastering the nano is a way to master the pico, directly by operating with nanoscale building blocks in picoscale feature sizes - between the blocks.

Cool!

[cciRRus]

Japan's NEC Electronics has developed a technology to make advanced microchips with circuitry width of 55 nanometers, or billionths of a meter...

Great, we'd be seeing Japanese nano MP3 players real soon! That should give Apple's iPod Nano a run for their money.

Re:Where's the Nanotech?

[aXis100]

AFAIK, nanotech was origonally about the construction of componets from the atom and up.

Whilst we may be building small things, it's really still chemistry and lithography that we're tinkering with. Only a few scanning tunnelling microscopes are actually building anything one atom at a time.

Nano...

[Spy der Mann]

Oh, did I mention that you gain less and less from going smaller
because more signal is wasted as heat.

Unless of course, you're optical transistors, nanotubes, spintronics and all that nano stuff that hasn't been applied to electronics yet.

Re:This sort of things always worries me

[chris_eineke]

Your fears have been fictionalized in "The Diamond Age, or: a young lady's illustrated primer", by Neal Stephenson. Read it. It's awesome.

Actually.. two 45nm plants

[Memophage]

Intel is in the process of building one plant (Fab 32) which contains 45nm processes in Chandler, AZ, and just announced plans to build a second 45nm plant (Fab 28) in Israel.

See for yourself.

Nice press, but these chips ain't cheap

[smilindog2000]

Finer circuitry decreases the size of a chip and cuts per-unit production costs... NOT!

Moore's Law is showing it's age... The cheapest transistors in the world are not build in 65nm. They are built in 180nm, a much older process.

In China, you can get 8-inch 180nm (.18u) wafers for $600. Today, a 90nm 8-inch wafer is more than 4X more expensive, and you cannot yet buy 65nm wafers. The cost per transistor is actually higher! And people wonder why we're taking our time to move to finer geometry processes!

EH&S issues?

[trolleywobbles]

I'd be interested in hearing what the course covered with respect to environmental, health and safety issues around nanomaterials. While these new materials bring interesting properties, they could also present some interesting, unexpected health hazards. By virtue of their size, nanoparticles can cross the blood/brain barrier. For some materials this new route of entry could be the difference between toxic and nontoxic. Materials that previously were thought of as nontoxic in the micron and above particle range could now have toxic effects. - Material data safety sheets generally don't consider a material's particle size, except to state "dusty" type warnings.

That the nanoparticles can have this new route of entry is proven - that this results in new toxic effects for previously nontoxic compounds is not (at least not that I've seen in the lit) - so there may be no issue - or there may be a big issue. Hopefully we don't find out the asbestos way where we make the material ubiquitous then be stuck with huge remediation and civil lawsuit issues!

Re:Where's the Nanotech?

[Zobeid]

Nanotubes and buckyballs aren't nanotechnology, as I see it. They are precursors of nanotechnology. They're getting ready for nanotech, working towards nanotech. . . And they can indeed be useful and profitable in their own right. But with regards to actual nanotech, we aren't there yet. And I never said that "no one" is investigating nanotech. A great many people are investigating it and working on the problem. They just haven't solved it yet.

As for the Ad hominem argument. . . ? Oh wait, I see. You think I'm assuming that because some people use the word nanotech as a meaningless buzzword, I'm then concluding that *everybody* who uses it is discredited.

No. I didn't say that. I freely and happily admit that there are people and companies researching real nanotechnology. But I stand by my statement that those companies aren't turning out any useful products yet, and they probably won't for several years at least. I follow this stuff, I'm not just pulling these assertions out of thin air.

Real nanotechnology: The "nanocar" they made at Rice University qualifies. It has multiple moving parts and is made with true atomic precision. It's about as simple as a machine can get, and it doesn't do anything useful, but it's undeniably nanotech. This is the stage we're at in nanotechnology research, right at the very beginning. If you compared with computer technology, for example, this is like trying to invent the first transistor.