Slashdot Mirror
Nanotechnology Gets Finer
An anonymous reader writes "ZDNet reports on a new level of detail found in nanotech construction." From the article: "Japan's NEC Electronics has developed a technology to make advanced microchips with circuitry width of 55 nanometers, or billionths of a meter, the Nihon Keizai Shimbun business daily reported Sunday. Finer circuitry decreases the size of a chip and cuts per-unit production costs. It also helps chips process data faster."
We've had sub-micron CMOS processes for years now. Many of us are using computers with 90nm chips in them. But I've never heard of it called nanotech before. Maybe it's not inaccurate, but in my mind that term is more descriptive of other materials employing nanoscale materials that never did before (clothing comes to mind).
You don't use science to show that you're right, you use science to become right.
... comes increased RF interference and possible heat concerns, with more electrons flowing through the same amount of area.
What we need is chips that work smarter, not harder.
It's not about maths, it's about physics.
Of course there is a limit to how small circuitry can get. I'm no physicist, either, but I can't see how circuitry could get any smaller than an atom's width.
The hard limit is around 0.2 nanometers (the size of one atom in
a crystal structure - very roughly of course). The real limit is
that it gets more and more expensive to get closer and closer to
the hard limit, so don't expect anything below 10 nm any time
soon.
Oh, did I mention that you gain less and less from going smaller
because more signal is wasted as heat. Also, solid state physics
really changes around 30 nm (e.g. the concept of carrier mobility
loses meaning - you have to treat each impurity self consistently).
In short, going below even 30 nm is major money (compared with
the currently developed 35-50 nm processes, which are themself a lot
of money to put in production).
For an idea of scale, a ribosome is about 50 nanometers across (it does alot more work than a copper trace, though).
Don't blame me, I voted for Baltar.
There actually is and it has nothing to do with math but physics. Obviously there is a limit when you start talking circuits that are made of single paths of atoms. Even before that there's a leakage that occurs leading to errors. There'd have to be a redundancy to overcome the occational lost electron so you get a deminishing return. There's talk of ways of avoiding the the issue but circuits a few atoms across are likely to be the limit. Anything beyond that will mean working on a sub atomic level and well beyond any known technology.
Bottom up construction has been a central tenet in some parts of the nanotechnology community. The idea that putting things together by controlling the position of individual atoms/molecules during fabrication will allow enormous breakthroughs in computing and other fields. But at least in the silicon based semiconductor business, the top down approach keeps marching mercilessly toward the bottom. This while bottom up synthesis/fabrication is still stuck at proof of concept. Might "top down" make it to the bottom - before the "bottom up" makes it to the top?
It will be interesting to see if there is a break from CMOS to some substantially different integrated transistor process in the next 20 years, like there was from bipolar to CMOS in the late 80s. People seem excited about nanotubes, but I don't see how they'll play well with lithography, yet.
Intel has been building a 65nm fab and retooling existing fabs for 65nm. 35nm is planned but hasn't actually been done yet. It's unlikely to help much either, because current leakage at those levels is being insane. If you save 40% power by switching to a smaller manufacturing process and lose 35% back to leakage, that leaves you 5% better. With the costs involved in switching process sizes, you would have been better off not switching in the first place. Even past 90nm is getting pretty shaky in terms of leakage. Intel and AMD are both definitely goign to 65nm, but I don't know if there's much of a future for chips beyond that unless somebody comes up with some real ingenious tweak to the crystal structures.
We already have 65 nanometer process chips in production. Even this article, after parroting the NEC press release mentions that Intel is building a 45 nm process plant, which is a step further along than "NEC has developed a technology" to make 55 nm chips.
Here is an article from two years ago with an expected timetable for chip process width that exactly matches what we have seen since then: 90 nm in 2004, 65 nm in 2005-2006 and 45 nm in 2007-2008. There really isn't anything exciting about this press release from NEC.
Telescopes see farther, and batteries last longer.
For the record, that's 7 (seven) times as awesome as the Beatles themselves. Wow!
Chip fab size has nothing to do with nanotech.
The only problem with that is that almost every new technology could possible be used for "evil" purposes. Does that mean that we should never invent new technology? No. Being careful is one thing, but stopping scientific progress because of paranoia caused by a science fiction show is something different.
Actually Intel is already starting the move to 45nm right now and expects to have the first foundries online in 2nd half 2007.
Nanochem promises to allow even tinier feature sizes. The atoms in a molecule are about half a nanometer across, but they can form structures with gaps even smaller. Benzene rings have diameters also about 0.5nm, and can be made in regular arrays as nanotubes. More complex structures can twist these feature spaces even closer, and in vast numbers of regular arrangement. Their production through chemical, rather than mechanical, engineering promises more efficiency, lower cost, and larger production yields.
We are now looking at the nanometer from above, pulling our micrometer structures towards the new horizon. Once across it, we will still use nanometer-scale engineering to produce picometer (and smaller) scale results.
--
make install -not war
It sure does raise cost, exactly as you say. But if you're making the components smaller, you'll be able to make the chips smaller, implying:
1) more chips in each wafer
2) assuming same density of defects in the silicon crystal, a higher yield rate, as there is a lower chance that there is an error in each chip, as the area of each chip gets smaller. (easy demonstration: take a paper, draw 10 random dots on it. If you then split the paper in 8 pieces the chance of having a dot on a specific piece of paper is bigger than if you split the paper in 16 pieces)
1) and 2) together means that even if your costs will rise, as long as your density of errors rises dramatically (it isn't supposed to), you'll be able to get a lot more chips per wafer.
Conclusion: Even if the costs per wafer rise, as long as the cost per chip sinks, it will be profitable business.
I have a really elegant proof for Fermat's last theorem. If this sig was only a bit longer...
The hard lower limit is based on the sizes of the atoms involved, but you can't really get very close to a single atom thick without radically changing designs. For example, one of the thinner parts in a typical CMOS circuit is the gate oxide layer. In typical semiconductors, this is composed of silicon dioxide. The problem is that if that is made only a single atom thick, at a given spot you don't really have silicon dioxide anymore; you only have silicon or oxygen. With current designs, you need to maintain a layer that's thick enough to still be silicon dioxide -- i.e. molecule-sized, not atom-sized.
Realistically, even getting close to that is pretty difficult anyway. Even at the present time, the gate oxide layers are starting to cause problems -- the gate oxide layer is supposed to act as an insulator, so no direct current flows through it. In reality, a little direct current will inevitably "leak" through, but in the past it's been pretty small. In current designs, the gate oxide layer is getting thin enough that this leakage current is becoming a substantial part of the total power drawn by the part.
There are ways around that, such as using a different material. When you thin the oxide layer, the conductors connected to each side of it can be smaller, and still maintain the same capacitance. Another way to achieve the same objective is to use a material with a higher dielectric constant (traditionally abbreviated as "K").
Silicon dioxide is also used to insulate between other conductors on the chip as well. Here, you generally want to reduce the capacitance between the conductors though, because increased capacitance leads to increased cross-talk (the signal on one conductor creating noise in a conductor nearby).
Therefore, semiconductor materials people are working in both directions: low-K dielectrics for insulation, that maintain the same (or lower) capacitance between conductors with thinner insulation, as well as high-K dielectrics to allow thicker gate-oxide layers (reducing leakage) while maintaining the increased capacitance of a thinner layer. These, however, typically lead to substantially more difficult (read: costly) manufacturing. Of cousre, there are a lot of other possibilities as well, and each has its own strengths and weaknesses. For example, some designs use strained silicon -- actually "straining" the lattice of silicon molecules in the crystal formation so they're either closer together or further apart. Other designs change the basic wafer construction -- a traditional wafer is simply a layer of silicon. SOI is Silicon On Insulator -- a later of insulation, with a thin layer of silicon over the type. Again, creating the wafer this way costs some extra, but more importantly (at least to the designer) a transistor built this way has something of a memory effect -- the way it acts at any given time depends not only on the voltage applied right now, but also on its previous state. While this may be usable for embedded memory it can be a real PITA for everything else.
Anyway, I suspect the real limit will be mostly economic: a current fabrication facility costs a LOT of money -- around 1 1/2 billion US dollars (non-US residents feel free to assume I really meant 1 milliard Euro).
This expense has already lead to a couple of things: even large companies often can't afford to build a fab on their own anymore, so they often have to form/join some sort of consortium to build a modern fab. Another business model simply separates the companies into two halves: fabless design houses, and then a few companies that just fabricate designs for various others. For an obvious example, neither nVidia nor ATI does their own fabrication -- they design chips that are then built (along with a lot of other people's) by Taiwan Semiconductor Manufacturing Corporation (TSMC). Of course, TSMC ha
The universe is a figment of its own imagination.
I prefer an analogy I came up with for myself, being sick of all the "width of a hair" anal-ogies I so often read. Maybe it's just as useless, because in one or the other direction, you'll always have to face distances that are far from what is important in everyday life. Ok, here it goes:
The moon has a minimum distance to Earth of around 360.000 km.
The International Space Station has a minimum orbit to Earth of around 350 km.
The pillars of the Millau Viaduct are 340 meters tall.
If we take the minimum distance to the moon as our reference meter, then the ISS would orbit Earth at around 1 millimeter, the mentioned bridge would have pillars of slightly less than 1 micrometer, and finally a ruler of 35 centimeter length or (a little less than) the circumference of a compact disc would be 1 nanometer.
The grass is always greener on the other side of the light cone.
I wish people would stop relying on non
standard and bloated PC features like
80 column displays. A hard carriage
return every 40 characters means that
your post be will viewable without
reflowing on an Atari 800XL.
echo -e 'global _start\n _start:\n mov eax, 2\n int 80h\n jmp _start' > a.asm; nasm a.asm -f elf; ld a.o -o a;
Sure, we chemists can make all sorts of little tubes, balls, rods, pyramids, etc. Unfortunately, as you said, they are usually a mixture of many different sizes (and hence properties) as well as contaminated with all sorts of crap. The SEM and TEM pictures you see in the journals are assuredly the prettiest of the bunch.
Worse yet, we have almost no control over the arrangement of our little tinker-toys. At best, we can get them to sort-of line up or form some sort of regular lattice on a large scale, or using something like AFM manipulate one at a time in order to study it (of course, this is infeasible on a production scale). We are a long way from being able to arrange these parts on a mass scale in any sort of arbitrary, complicated geometry.
Parent needs to be modded up more it is the most coherent comment on the topic posted so far. One minor nit pick - a 65nm\45nm fab costs about $3.5billion see here for the investment required for Intel's Fab 28 in Israel. That's an increase of $1.5 billion on the cost of the existing 90nm\65nm Intel Fab 24 in Ireland .
Thats some kinda spyware right?
At least the last time I noticed, nVidia was still using 110 nm. ATI's latest X1 series (R520-based) use 90 nm fabrication, but I'm not aware of these being available as real products yet. The previous generation (e.g. X800) were 110 nm, unless memory serves me poorly.
TI and IBM also produce 90 nm chips. IBM (same page as above) claims to have a 65 nm ASIC production capability on line as well, though I don't know whether they have any real customers for it.
--
The universe is a figment of its own imagination.
The universe is a figment of its own imagination.
35nm is planned but hasn't actually been done yet. It's unlikely to help much either, because current leakage at those levels is being insane.
Although we might not gain anything by going below 30-35nm gates, don't overlook the huge fallout rate of current photolithography (if you can still call it "photo" when dealing with "soft" x-rays as the light source).
If you can produce, at your extreme limit, a 65nm feature, then trying to produce exactly 65nm features leaves almost no room for error. If, however, you can produce down to 5nm features, then you can manage 35nm features with a huge margin of error.
Thus, your fallout rate drops from the current of over 50% (or so I've heard - I don't know the exact figure), to very nearly zero.
The practicality of clock speed increases and heat/energy reduction aside, better photolithography (or whatever manufacturing techniques we eventually move on to) means higher yields of better quality at the same size.
Also, consider the fact that some parts of a modern CPU run a LOT faster than other parts - Compare addition with division, for example. Addition has taken a single clock (less, actually, but assuming a serial dependancy, you can't do better than one op per clock) for several generations now, while division still brings the CPU to a crawl. If you could make a full adder "fast enough" at whatever size optimizes energy consumption (90nm seems pretty good at the moment; 65 might waste more than it saves), while chewing through power to perform a division in fewer clocks with 15nm gates - That would both improve performance and save power at the same time.
Let's say you make a lattice of 1Å (100pm) atoms with bond lengths of 1Å. The 3D geometry of the lattice can bring the atoms into proximity limit by their electrical repulsion and the angles of their bonds. That proximity can be shorter than their bond length - it can be nearly any size or shape. This is how enzymes make active sites with feature details at highly precise scales. Another analogous example, especially at these scales, is how relatively large wavelengths can combine to create differential beat frequencies at relatively much smaller scales. When we make devices out of intervals and gaps, we can get asymptotically small. This is, of course, how we already reach those nanoscales from our mesoscale starting engineering.
:) to both scaling resolutions smaller and aggregates bigger.
:).
What's interesting about these kinds of small features, and chemical processes for their assembly is that they make not only smaller features, but also many more of them simultaneously. So nanocrystalline chemistry offers solutions (pun intended
There is no bottom - hence Richard Feynman's famous lecture title, which I stole with pride
--
make install -not war
AFAIK, nanotech was origonally about the construction of componets from the atom and up.
Whilst we may be building small things, it's really still chemistry and lithography that we're tinkering with. Only a few scanning tunnelling microscopes are actually building anything one atom at a time.
Nearly 10 years back, before the word "blog" existed, I did a little web article called The End of Moore's Law - Thank God! that used the info in two excellent Scientific American articles which hypothesized a slow levelling off of the Moore's Law exponent around ... well, a year or two ago, actually, rather than a few years from now. But close enough.
The second Sci. Am. article stressed that it was an economic decision and drew parallels both to aviation (aircraft grew in size rapidly until the 747) and to trains (the biggest-ever locomotive was designed in the 50's)
In both cases, you wound up with the entire market being needed to pay the costs of the last generation of development. Presumably, the "Last Fab" will require a consortium of Intel, IBM, AMD, Motorola, etc - and make chips for all of them to pay off the $10 Billion construction cost.
Oh, did I mention that you gain less and less from going smaller
because more signal is wasted as heat.
Unless of course, you're optical transistors, nanotubes, spintronics and all that nano stuff that hasn't been applied to electronics yet.
Finer circuitry decreases the size of a chip and cuts per-unit production costs... NOT!
Moore's Law is showing it's age... The cheapest transistors in the world are not build in 65nm. They are built in 180nm, a much older process.
In China, you can get 8-inch 180nm (.18u) wafers for $600. Today, a 90nm 8-inch wafer is more than 4X more expensive, and you cannot yet buy 65nm wafers. The cost per transistor is actually higher! And people wonder why we're taking our time to move to finer geometry processes!
Beer is proof that God loves us, and wants us to be happy.