Reduce Transistor Power Consumption

revelCyllufyalP writes to tell us that University of Kentucky researchers have discovered a way to reduce the overall power consumption of transistors. From the article: "In order to improve computer chips' performance, transistors' size and gate insulators have to be continuously shrunken so that more components can be packed into a single chip. Computer chip producers were hitting a wall in downscaling the transistors and gate insulators because of their inability to reduce the leakage current of the existing gate insulators. This new technique will help the chip producers to develop more powerful chips with low-power consumption."

Comments

Re:Woohoo

[0racle]

How could this not sound significant to the general users of this site. The latest Athalons and Pentiums use how much power again? If these guys patent this idea, I'm guessing it could make them quite rich.

size vs heat

[esac17]

What you have to remember about heat is that electronics only get hot because they are never perfect conductors nor perfect insulators {though we can make nearer-perfect insulators than we can conductors}. A perfect conductor will never get hot, no matter how much current you put through it, because the voltage drop across it will be nil and power = voltage * current. Nor will a perfect insulator, because this time, the current through it will be nil.

CMOS is based around two transistors, a P-channel FET which goes conductive when the gate is driven low, and an N-channel FET which goes conductive when the gate is driven high. The P-FET is trying to pull the output high and the N-FET is trying to pull it low. Both the gates are joined together, and this is the input. This is a simple NOT gate.

For a NAND gate, where any input 0 will drive the output to a 1, we have several P-FETs in parallel trying to drive the output high, and so many N-FETs in series trying to drive the output low. Each P-FET gate joined to an N-FET gate is one input. When they are all high, all the N-FETs turn on allowing the output to go low; when any one is low, the chain of N-FETs is broken, one or more P-FETs turn on, and the output goes high. For a NOR gate, where any input 1 will drive the output to a 0, we put the Ns in parallel and the Ps in series. You can make AND gates from NAND+NOT, OR gates from NOR+NOT, and any other combination you like. In fact you really don't need both NAND and NOR, because you can make either one out of the other; but it turns out they're equally as easy to make as each other in CMOS {not like many other technologies}.

In an ideal world this would never dissipate any power, since the input cannot be high and low at the same time so only one of the transistors will ever be on. In practice what happens is that the gates act like capacitors which take a finite time to charge and discharge. They do not switch instantaneously from conductive to non-conductive. So one stops conducting while the other is starting to conduct, and for a brief instant while the inputs are changing state both transistors are conducting a little. It's not a dead short circuit of course, otherwise something would give way ..... hopefully a fuse.

Now every time something changes state, you get a little pulse of heat. Which is why fast processors need cooling. Additionally, to make sure that the logic gate output has changed state before the next clock pulse, you need to make the gate capacitances charge up quickly -- which means using a higher voltage than you could get away with at lower speeds. But 2x more volts means 2x more amps means 4x more watts.

Smaller transistors should have less gate capacitance, and so be capable of switching more quickly.

Re:How do you reduce tunneling current?

[soundsop]

It's easy to reduce the tunneling current through the gate. All you have to do is increase the thickness of the insulator. Unfortunately, this has the detrimental effect of reducing the effective capacitance of the gate, which in turn lowers the amount of current conducted by atransistor of a given size (lowering the current also lowers the speed). To make up for the lowered gate capacitance, researchers have been trying to increase the dielectric constant of the insulator. I'm guessing that they're proposing a method to increase the dielectric constant of the gate insulator. The devil is in the details of improving the dielectric constant without screwing up later processing steps or reducing the mechanical integrity of the wafer, etc.

Summary:

1. To lower gate leakage simply increase dielectric thickness.
2. To make up for lost speed due to higher dielectric thickness, increase dielectric constant.
3. Profit.

Re:Chip insulator sas capacitors?

[Anonymous Coward]

You can use a high-k dielectric and get the same capacitance as a SiO2 layer. A good looking material is HfO2. Keep in mind that as transistors are scaled, the capacitance is scaled too -- thus your natural increase in speed.

The leakage is normally due to direct tunneling. Basically the silicon dioxide layer is so thin and the electric field is so high that electrons tunnel between the gate and the source/drain.

I think all this paper is about using some sort of thermal processing to make a higher quality gate and or oxide. Doesn't seem too Earth shattering to me.

Physics

[kf6auf]

A quick lesson in quantum physics:
Basically, tunnelling occurs because an electron can get from one side of a potential barrier to the other without ever being in the forbidden region (the width of the barrier, where the potential energy exceeds the total energy of the electron) due to it existing as a wavefunction that does not collapse until you observe it. Anyway, the chance of an electron penetrating a simple potential barrier like the gate of a transistor is a function of the height of the barrier (voltage applied to the gate), the width of the barrier (gate length), and the energy of the electron (voltage across transistor + electron thermal energy).

So ways to decrease tunnelling include:

• Longer gate, but slower. Wanting smaller transistors and faster speeds is the whole reason we're having this problem.
• Increase gate voltage or decrease transistor voltage. Unfortunately these two are coupled. They might not exactly cancel each other out, but they make things difficult.
• Decrease the thermal energy of the electons. There are a couple ways to do this. One involves liquid nitrogen; the other involves something like making electrons climb further out of their holes to become free (fairly easy by introducing impurities into the silicon), resulting in less electron energy and so less tunnelling. Also less current in general though, so this might be prohibitive for some other reason.

Just my $0.02 since if I knew for sure I'd be making 6 figures somewhere and not applying to grad schools...

Re:PlayfullyClever, eh?

[Anonymous Coward]

i checked the program at the 2005 International Semiconductor Device Research Symposium (http://www.ece.umd.edu/isdrs2005/program.html/) and sure enough, today at 4:35 PM, their paper is being presented: Dramatic Reduction of Gate Leakage Current of Ultrathin Oxides Through Oxide Structure Modification, Zhi Chen et. al, University of Kentucky

Re:Chip insulator sas capacitors?

[Antique Geekmeister]

Of course power flows through capacitors! You've got charges, you've got voltages, you have that charges flowing from one side to the other with a voltage on them in a certain amount of time, charge * voltage / time = power. If you couldn't transmit or modulate some power, you couldn't transmit or modify a signal. That's basic thermodynamics: if you can't transmit power, you can't transmit a signal.

The "work done" is, to some extent, recoverable when you change the state of the MOS transistor by discharging them. But that work is usually wasted and thrown away by simply discharging it to ground, then recharging it from the power supply, and that energy has to go somewhere and come from somewhere. But that can happen more in the power supply, and to some extent happens as electromagnetic radiation. You can't get rid of those two problems until you start playing with superconductors.

The heat and loss issues these researchers try to deal with are wasted work, trickle currents of keeping the transistor gate signals charged up as electrons leak away from the gate part of the transistor into the signal part of the transistor. They're nasty problems, taking constant current to keep even static signals active and wasting power as heat that has to be dealt with by some means.

Re:Cuts 75% of power usage in current generation

[Markus Registrada]

Switching current runs only when a signal changes. Most signals don't change in most cycles, but the transistor gates leak continuously. Furthermore, as the transistors get smaller, the capacitance per transistor goes down, but the gate current leakage goes up inverse-exponentially -- or did. So, the switching current really goes up only linearly with the clock rate, but there was no upper limit for the leakage current.

Re:PlayfullyClever, eh?

[Surt]

I don't really see how it's possible for the submitter to be fake. Either he submitted the story or he didn't. Apparently, he submitted the story.

Now, he might think the joke is that he's posting 'news' from a news aggregation site to a news aggregation site, but meta news is the only kind of news slashdot gets anyway, and that's what we come here for.

All in all, if he's scamming slashdot, he can only be doing it if EurekAlert is a fake, which it certainly doesn't look like at first glance, though I notice that in an unusual move for a meta-news site, it doesn't have links to originating information. That is somewhat suspicious. Still, if true, it's an incredible effort he's putting in just to scam slashdot stories.

Further, it would have to be a long term scam plan, since the UKY story in particular is real:
http://news.uky.edu/news/display_article.php?artid =844

So at best he's trying to build credibility as an article submitter for a later scam.