Reduce Transistor Power Consumption

revelCyllufyalP writes to tell us that University of Kentucky researchers have discovered a way to reduce the overall power consumption of transistors. From the article: "In order to improve computer chips' performance, transistors' size and gate insulators have to be continuously shrunken so that more components can be packed into a single chip. Computer chip producers were hitting a wall in downscaling the transistors and gate insulators because of their inability to reduce the leakage current of the existing gate insulators. This new technique will help the chip producers to develop more powerful chips with low-power consumption."

Comments

Woohoo

[matr0x_x]

This may not sound like that big a deal, but let me assure you this is very significant to wireless infrastructure enhancement. One of the biggest limiting factors in wireless devices is power consumptions, so this is great news for the industry!

How do you reduce tunneling current?

[Beryllium Sphere(tm)]

The press release says they're getting several orders of magnitude less tunneling current through gate insulators. But tunneling happens because some portion of the electron's wavefunction extends to the other side of the insulator. Whst are they changing that would affect the physics? Or are they fixing a different kind of leakage and getting the press release wrong?

Where's the news?

[Anonymous Coward]

As probably one of the few semiconductor geeks on /., I have to say: Where's the news? Gate dielectrics are always made with rapid thermal processing on current technologies. Basically, stick a wafer in a chamber, flow some gas, turn on some super-high intensity
lamps, heat the wafer to >1000C for a very brief time, grow a few atomic layers of silicon dioxide (or some variant that includes nitrogen), turn off lamps, cool wafer, take it out of chamber.

From what little info is in the press release, it doesn't sound like they're doing anything revolutionary, so I'm curious why they claim they can reduce gate leakage by so much.

It is already done, old news

[karvind]

Gate oxides in current microprocessors are around 1.2-2 nm and are grown using RTP (rapid thermal process). A furnace oxidation is too fast. So yes industry already uses rapid thermal anneal (as suggested in TFA) for their gate oxides. Can anyone tell how is the new ?

WTF is rapid thermal processing?

[arrrrg]

Anyone know? For once Wikipedia isn't much help.

PlayfullyClever, eh?

[Ospeovedizer]

So, did ScuttleMonkey not notice that the submitter's name was PlayfullyClever backwards? The one whose website says that the vast majority of /. posts are "blatantly plagiarized"? Although the news seems real enough to me, the submitter's name and website raised some pretty big alarm bells, especially since their site now says:

"okay, so we are going to win slashdot again, this time with a different game plan, keep your eye out for our new name.. it is VERY playfully clever."

Hmm... As I said, the news seems real enough, but the submitter is a fake.

Re:size vs heat

[soundsop]

Some clarifications:

Short-circuit current is only responsible for 10-20% of switching power. The rest is dissipated in the transistor through charging and discharing all the nodal capacitances (due to transistor gates, transistor diffusions and wiring capacitance). Since typical circuit styles are non-adiabatic, this charge/discharge power component would not go away even if we could completely eliminate short-circuit currents.

Making transistors smaller certainly reduces their gate capacitance but it also reduces their current drive by the same proportion. These two effects cancel each other out! So how can transistors get faster from generation to generation?

Transistors get faster by increasing electron mobility and/or increasing gate capacitance per unit area and/or reducing diffusion junction/sidewall capacitance per unit area/perimiter and/or reducing (local) interconnect capacitance since smaller transistors are closer together.

Re:size vs heat

[elgatozorbas]

They do not switch instantaneously from conductive to non-conductive. So one stops conducting while the other is starting to conduct, and for a brief instant while the inputs are changing state both transistors are conducting a little.

Even if they don't EVER conduct (even a little) at the same time there will be dissipation because the capacitance is charged and discharged all the time. Each of these cycles implies that some positive charge moves between the power supply and ground with the capacitor as an intermediate step. This is why the dissipation is proportional to the clock frequency.

That's Gate Leakage, but what about SD Leakage?

[trigeek]

From the little information provided in the article, it appears that this takes care of the gate leakage problem, which is great! However, it doesn't address the Source-Drain leakage, which is a larger issue for current process technologies. Gate leakage isn't forseen to be a significant problem until 45nm.

This just tells us that future technologies are not going to have twice the leakage power as current technologies. This doesn't mean that future process technologies are going to have less leakage power than the current ones.

that is so very not right...

[YesIAmAScript]

Yes, power dissipated is V*V/R or VI And yeah, smaller transistors have lower resistance. But smaller gates mean less power, not more. You need less current to move the charge in and out of a smaller transistor (since the charge is smaller). So the "I" in the "VI" can go down. Well, that "I" is really a "V/R" (current across a resistance), so lowering that I really means you can reduce the "V". And since the total power is V*V/R, that means the total power used drops drastically.

Let me explain it a little better because I think I even confused myself.

Power is V*I. The I is V/R. Lowering this R means the V/R value does get bigger (current goes up). But also, since the I only needs to be sufficient to fill or drain a gate in a given amount of time (one cycle), you can reduce the V until V/R is a more reasonable value. And when you lower that V you're also reducing the other V in the power formula (V*V/R), so in fact instead of power going up, it goes down greatly.

For a much easier corollary, look at AMD's 130nm CPUs against their directly equivalent 90nm versions. The 90nm versions take half as much power.

Today's nuclear CPUs are mainly because there are so many transistors switching so fast in such a small space. If you built an old-type CPU using 90nm technology (like an Z80 or something) it would take far far less power than the old ones, which ran off of +5V (plug that into V*V/R!). Additionally, current CPUs have a lot of leakage current, something that CMOS didn't have a problem with until we got to sub 180nm processes. Compare a current CPU to an old NMOS or even ECL processor. You'll see how leakage was a problem before and how much of a savior CMOS was.

Additionally, the megahertz race is not over. It may not be the current concentration of vendors, but as chips go to smaller and smaller feature sizes, they naturally get faster. So even with little concentration on speed, we'll still see a rise in individual core speed.

A 1000-thread (simultaneous) chip is a ridiculous idea. That means you have to duplicate every transistor in the chip (like registers) 1000 times. That makes no sense. You will never reach the same speed as current single processor chips with a 1000-thread CPU (at least not right now). A small number of cores is a better idea at the moment.

Re:that is so very not right...

[william_w_bush]

a: I think I misspoke. When I said that at smaller feature size, resistance goes down, I was also considering leakage as a failure of resistance. You're right, the current 90nm designs do use less power, the amd design in particular because it uses SOI to compensate for increased leakage, while I don't believe intel has soi on its chip line yet. At these scales, execution tends to matter as much as size, and my earlier point of blindly scaling down in hope of finding more gains from the magical process shrink becomes much more of a challenge.

2: Also, in a 1000-thread chip, not nearly all the parts of such a chip would have to be replicated. Much of current superscaler design relies on scheduling for as efficient usage of pipeline segments as possible, to allow for the maximum chip usage. This same approach could work, by turning l1 cache into an effective register file, and simply having a part of the chip whose role is to schedule prioritized register sets to the requisite resources. At the extreme this could even allow decoupled pipelines, such that the decode, memory load and IO intructions are executed in a primary stage chip dedicated to preprocessing and high wait state instructions, then passed on via HS interconnect to 1 or more secondary processors to perform the actual arithmetic, even allowing whole chips to perform the ancilliary functions such as the sound or GPU today, while being tightly coupled to the memory and processor state.

My point is that from this point on, threading will scale much faster than clockspeed. Even now, it is easier to make a second core than to double the clockspeed for the faster processors, and unless the leakage issue from tfm is solved soon this won't change.

Plus, once you have the right programming language support, with auto-parallelizing iterands, and self-dispatching async subroutines, who needs a fast chip, the actual instruction pointer, the current limiting factor, becomes meaningless, with all actual work being done parallel automatically, dependencies and resource sharing solving themselves by language design. A 1Ghz multithreaded chip can be as effective as a 4.0 Ghz prescott today, without even including the specialized instructions (SIMD, fast fp) that can boost actual efficiency through the roof, and be compiled in as static asynchronous subroutines dispatched parallel to the "main" thread.