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AMD Licenses Z-RAM Technology
ZuperDee writes "It appears AMD has licensed Z-RAM technology from Innovative Silicon for possible use in future processors. According to the article, this could lead to caches about 5 times denser than the SRAM that is normally used right now. C|Net says they will probably make the announcement on Monday."
It's a single-transistor capacitorless memory cell using the "floating body effect" of silicon on insulator (SOI) devices. Presumably stored charge in the gate affects the operation of the transistor in a way that can be used to store and read a bit, but I didn't feel like registering to read the white paper. The new memory should be six times denser than SRAM and twice as dense as DRAM.
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This is another article covering the licensing which was on digg.com earlier http://www.eetimes.com/news/semi/showArticle.jhtml ;jsessionid=V2AQAAYC3GVIQQSNDBESKHA?articleID=1771 01749
http://www.google.com/search?q=zram
5 18&id=5434
A nice techy article about how/what makes ZRAM special. It goes in-depth about the things you mention. http://www.cieonline.co.uk/cie2/articlen.asp?pid=
Obligatory Wikipedia Link
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They can, but probably won't.
As many like to point out, Intel often shows a "Not Invented Here" attitude.
It took a while for Intel to adopt copper interconnects, and they did that quietly when they finally caved.
As far as I know, they still aren't using Silicon On Insulator.
"Everything you know is wrong. (And stupid.)"
Moderation Totals: Wrong=2, Stupid=3, Total=5.
Rambus is not a way to store information on a chip, it is a proticol designed to transfer data between storage spaces using packets and a bus. This is a constrast to SDRAM which transfers data by synchronously indexing then caching a strip of data and copying it to or from the chip's cache. Z-Ram on the other hand is a way to store information on a chip just like DRAM or SRAM. Z-Ram makes no demands as to how information is transfered, it may theoretically be done using the Rambus system (making RZRAM rather than RDRAM) or more likely using the Double Data Rate Synchronous Ram system (making DDR SZRAM as opposed to DDR SDRAM). In this case it is not intended to be used as system ram at all but on-die cache. Thus it will not have to use either of these systems since it (as cache) will only need to interface with the CPU and MMU. Such a system will have no impact as to what ram someone may use and will make no archetectual differences outside the die. Thus the Rambus comparison is completely pointless. If you had even read the summary properly you would know that.
When Argumentum ad Hominem falls short, try Argumentum ad Matrem
Because system RAM is built from capacitors, not transistors. Otherwise, RAM would be exceptionally expensive. Building substantial amounts of memory out of transistors takes a *LOT* of transistors. something like 20 transistors for one BIT. This is why the caches of modern CPU's consist of the bulk of the CPU die. This is also one reason why cache is faster than RAM, because transsitors are faster than capacitors...
Cell processors will not be powering new desktops in the future. I would bet money on that. Because of IBM's track record, the cell will probably be 1. Overpriced 2. Underperforming They may have inked sweet deals with game console manufacturers, but I don't see what advantage it has on the desktop. The future of the desktop seems to be in mobile devices such as laptops and handhelds.
Well, it's a sign that market leader Intel has over the decades drifted more towards marketing machine mentality, while challenger AMD has stayed somewhat truer to its engineering roots.
Intel went for Itanium, while AMD went for 64-bit x86.
Intel went for Rambus, while AMD went for DDR and HyperTransport.
If you look at the multicore technology AMD is researching, it looks better than Intel's multicore.
I'll acknowledge that Intel recognized the value of wireless ahead of AMD, although dedicated wireless chipsets are obviously better than Centrino anyway.
I'm just glad that healthy competition is there, to make us consumers the ultimate winners.
If I recall correctly, an SRAM memory cell only contains 6 transistors: two access and 4 "internal" (essentially forming a flip-flop), while a DRAM cell contains one n-channel MOSFET (access transistor) and a capacitor. DRAM is also slower because it is is dynamic (hence the D) and must be rewritten. Plus, with dynamic ram, you need to refresh the contents every 5-10ms because of leakage current off the capacitor through the transistor.
Considering a standard DRAM cell (there are many variations, but what I gave is pretty standard I think) is tiny in itself, I'm curious as to the setup of this Z-RAM and if it's static or dynamic (probably dynamic). Unfortunately, the article gives no technical information.
In a nutshell, on a CMOS transistor on an SOI process (such as used by AMD and IBM, but not used by anyone else that I can think of... Intel, TI, TSMC, NEC, Samsung, etc), the delay of the transistor (how fast the transistor is) depends on the history of the signals that were applied previously to the terminals. So the transistor has a memory of previously applied values. Which, now that I write this, seems like it's obvious that this would make a possible memory storage element, but normally this "feature" is a major pain - because it's difficult to track the history of signals on a transistor using current CAD tools for, for example, determining the speed of the final design, you have to assume the worst case (so that your chip works no matter what).
0 0076+body+hysteresis+soi&hl=en )
So normally this "feature" is considered a liability, or at least something that designers wish could be an asset but which is too hard to utilize effectively and is thus ignored.
In more gory details, this exerpt from EETimes explains it pretty well:
( http://ww.eetimes.com/issue/bb/showArti...D%3D573
In partially depleted MOS transistors -- the only kind used in production SOI today -- the body of the transistor is a small, electrically isolated piece of silicon trapped between the active portions of the transistor and the insulating layer underneath. If this body is allowed to float, it will take on a voltage determined by the capacitive coupling between it and the other portions of the transistor. But the voltage -- or, more properly, charge -- on this floating body can affect threshold voltage, and hence the drive current, of the transistor.
Ideally, the floating-body effect can deliver a formidable performance gain. Two circumstances arise from that gain, Soisic's Pelloie said. First, the voltage on the body influences the transistor's threshold voltage. "If you switch the gate of the transistor from off to on, then the body potential increases, which yields a decrease of the threshold voltage and then an increase of the drive current," he said. "The switch is then faster than in the bulk CMOS case, where the body is grounded."
The second effect is another mechanism for influencing the threshold voltage. "When you use stacked transistors in a gate, like NAND, NOR and any other combinational gate with multiple inputs, the body-to-source voltage of the transistors corresponds to a forward-bias condition, and the threshold voltage is lowered," Pelloie said. "For bulk CMOS or in a grounded-body situation, if the source has a high voltage value, for instance Vdd [the power supply voltage], the body source voltage then becomes - Vdd and the transistor body source junction is reverse-biased." That increases the threshold voltage and lowers the drive current. Analyzed at the circuit level, he said, these two SOI advantages are combined and globally yield a higher-speed operation.
But there is a catch to these threshold-voltage-lowering mechanisms, as Pelloie explained: "Since the body is floating, it follows the variation of the other terminals of the transistor. The body voltage never keeps the same value, as the transistors are, most of the time, switching in normal operation mode. This results in what we call the history effect: The propagation delay and some other features of the gates depend on the history of the signals applied to their terminals."
-------- end EETimes snippet -----
It will be interesting to see how this particular use of the floating body effect scales as we continue to move to 45nm and beyond. It will also be interesting how it handles low-voltage quantum-induced soft-errors. Also, similar to DRAM, this type of memory will need to be refreshed - if AMD uses it in a design, it will interesting to see how the impact of refreshing, and trying to read a very small effect and amplify it to make a signal will impact the speed of the devices when used in a large cache array.