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Intel Ships Core Duo-based Xeon

Posted by ryuzaki0 on from the new-chips dept.

diegocgteleline.es writes "According to The Register, Intel has begun shipping a power-efficient dual-core "Xeon LV" and claims that it consumes no more than 31 W running at 2 Ghz, with a 667 Mhz frontside bus and sharing 2 MB of L2 between the two cores. The new chip has "four times the performance-per-Watt of its existing 2.8GHz LV Xeon CPU", not surprising given how slow and power inefficient those CPUs were. While this looks like a move to make AMD shares continue yesterday's tendency, it looks like Intel is starting to catching up?"

45 comments

  1. Finally, some competition by Btarlinian · · Score: 2, Insightful

    Intel has been losing so much market share in the server space recently. Maybe now they will be able to recover a little. Although, I'm not sure if this will compare to AMD's top offerings.

  2. Power efficiency is all good and nice but... by dc29A · · Score: 2, Insightful

    This CPU is crippled by a shared 667 mhz bus while the Opteron isn't.

    1. Re:Power efficiency is all good and nice but... by 2nd+Post! · · Score: 2, Insightful

      Yes, but isn't this also true of the other Core Duo solutions that happen to be equivalent in performance to Athlon/Opeteron CPUs?

      --

      GPL Deconstructed
    2. Re:Power efficiency is all good and nice but... by shadow0_0 · · Score: 1

      Exactly. And why are they sharing the same cache? Would it make more sense to have separate cache?

    3. Re:Power efficiency is all good and nice but... by Anonymous Coward · · Score: 1, Insightful

      You have to trust that these guys know what they're doing. It's fast enough now, and they've got legroom to keep the upgrades (cash) coming in. Intentionally crippling chips has been going on since the celerons. In this case though, they're in the enviable position of being able to cripple on of their flagship products.

      I'm looking forward to AMDs response to these impressive (at least in the preview) chips.

    4. Re:Power efficiency is all good and nice but... by xenocide2 · · Score: 1

      I have no idea if this could ever possibly be thread safe, but it might be possible to have incredibly fast IPC via the cache.

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    5. Re:Power efficiency is all good and nice but... by lsd · · Score: 4, Insightful

      Not exactly. On a single CPU system it makes little difference, but on 2 CPUs and up, the Opteron's NUMA architecture based on multiple memory controllers and high-speed point-to-point links between CPUs, each of which is quicker than the 667Mhz that these Core Duo-based Xeons will share for all memory access and cross-CPU traffic, is a huge win. As you can imagine, that win only increases when you move up to even larger systems.

    6. Re:Power efficiency is all good and nice but... by IntlHarvester · · Score: 1

      I don't believe that any common OS treats 2x or 4x Opteron systems as NUMA.

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    7. Re:Power efficiency is all good and nice but... by wolrahnaes · · Score: 1

      The AMD64 versions of Windows (both XP and Server 2003) and Linux do NUMA on Opterons. Common enough for you?

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    8. Re:Power efficiency is all good and nice but... by (negative+video) · · Score: 1

      And I have actually written NUMA-aware software (a cellular automata simulator) for Linux on Opteron. It's very easy to write and works well.

    9. Re:Power efficiency is all good and nice but... by jmv · · Score: 1

      With a bit of OS support (context switch and all), I think it's possible and actually has already been done (could be wrong, though).

      --
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    10. Re:Power efficiency is all good and nice but... by JollyFinn · · Score: 3, Informative

      While it might be "cripled" by FSB.
      Its faster than fastest opteron on perl and circuit layout part of spec int. And looses badly on chess ;)
      In overall its EQUAL to fastest dual core opteron on spec int.

      The fact remains that FSB is just ONE variable in huge nets of variables in performance equation.
      Using more cache means less memory accesses outside chip, using better prefetcher, helps memory access and soon, the off die memory accesses take such a small fraction of time, on MOST software that ondie memory controller vs FSB becomes non issue. [The percentage of improvement from ondie becomes less important than being flexible at new memory technologies on old sockets.]

      And memory accesses only take part of the time that must be improved other part is improving core, which part is often more important than improving the offchip memory accesses when there is enough cache. [depends on code].

      Take one thing that competitor can potentially do some what faster means nothing if you separate it from all the other aspects of CPU.

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    11. Re:Power efficiency is all good and nice but... by IntlHarvester · · Score: 1

      Thanks for the correction!

      --
      Business. Numbers. Money. People. Computer World.
  3. Apple's new XServe by Anonymous Coward · · Score: 0

    Here in just a bit I bet apple announces the new XServe and PowerMac lines based on this processor.. Sad really.. Apple is going "power friendly" and leaving cluster people who only really care about performance in the dust..

    1. Re:Apple's new XServe by Anonymous Coward · · Score: 0

      Huh?

      "Cluster people" care about power efficiency just as much, if not moreso, than raw performance. It's not cheap operating a chip that requires 120 Watts to keep running. If the average lifespan of a cluster is three years, and the difference between these two chips is 100 watts, and you pay $.08 per KwH, you save $210 over the life of the chip - and that excludes cooling costs.

      Plus, these chips offer more performance than the equivalently priced Xeons do anyway. I don't see your point at all.

    2. Re:Apple's new XServe by Wesley+Felter · · Score: 3, Interesting

      The inevitable Woodcrest-based Xserves should satisfy those people who only care about performance. Or they could just buy Opteron servers today.

    3. Re:Apple's new XServe by hpcanswers · · Score: 3, Interesting

      The whole reason people buy clusters instead of a specially built system like Cray's is for the cost. Running a large (hundreds of nodes) cluster costs upwards of tens of thousands a year for electricity and cooling. Energy efficiency is definitely warranted in this case. It's the same reason IBM's BlueGene employs 700 MHz PowerPC processors. http://en.wikipedia.org/wiki/Blue_Gene

  4. Bogus claims... by Anonymous Coward · · Score: 0

    Intel has been losing so much market share in the server space recently.

    Please provide hard numbers to back up your comment from a reliable source. I work for an unnamed OEM and we ship both Intel and AMD servers. Quite frankly, the demand for AMD hasn't been all that great and were it not for the kick backs AMD gives us, we'd drop their systems. Both percentage-wise and hard numbers show our AMD systems suffer from inferior component failures far more often than Intel systems. Once we start demanding tighter QA, the price of AMD server was greater than Intel systems in the same space. Our customers keep voting for Intel.

    1. Re:Bogus claims... by Scott+Lockwood · · Score: 0, Flamebait

      Bullshit. Say who you are, and back up some of what YOU are saying with hard numbers, or FOAD.

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  5. Sorry Intel by 9mm+Censor · · Score: 1, Informative

    Opterons set the bar at 64bit processors for server chips.

  6. Editor commentary is weak by Anonymous Coward · · Score: 0

    I guess maybe we don't realize that shareprice != quality of product.

  7. A start, but no 64-bit? 667 Mhz front-side bus? by DonChron · · Score: 5, Insightful
    Intel's going to have to do a lot more than this to catch up to AMD in the server space. This is an improvement in power consumption, but they're still gated by the front-side-bus architecture which only gets more crowded as you add processors. And 32-bit only... they must really be feeling the heat (lack of heat?) from the Opteron to release a new 32-bit server processor when mature 64-bit OS's and applications are available. Even Microsoft x86-64 Windows and SQL Server products have been out for months, while x86-64 Linux and Linux apps have been out for years.

    It looks like they're desperate to show some progress...

  8. What's new? by Andy+Dodd · · Score: 2, Interesting

    The article specifies a TDP of 31W, a total of 2 MB cache (1M per core), 667 MHz FSB, and a clock speed of 2.0 GHz.

    How is this different from the Core Duo T2500? From the looks of it, there is none.

    --
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    1. Re:What's new? by tomstdenis · · Score: 2, Informative

      Just a correction, if I'm not mistaken that's 2MB of L2 ... period. Not "per core". That means internally the bus between the cores and the cache is shared. Chances are there is some facilities to "prefer" a region of the cache [e.g. dual-ported] but as far as I've seen logically it's a 2MB cache both cores can access.

      Tom

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    2. Re:What's new? by bdipert · · Score: 1

      This is code-named Sossaman. It's a Core Duo/Yonah variant (good eye!) with multi-processor support, along with virtualization support.

    3. Re:What's new? by Andy+Dodd · · Score: 1

      Yonah supposedly also includes virtualization support. (It was supposed to, I haven't seen any confirmation either way whether or not it actually is in there. Anyone know if it would show in /proc/cpuinfo and what specific flags I should look for? I've got a T2500-based laptop in the other room.)

      Also I have not seen any confirmation yet that the new Sossaman actuall supports multiple CPU packages per system. Intel's comparison page for the Xeons lists all of the Xeons I've tried as being MP capable, while the new Xeon LVs are only listed with a system type of "DP" - the die/package already HAS two processors though.

      As to the issue of shared vs. independent cache between the cores - yes, it looks like while most third-party specs for the Yonah list it as "1M + 1M", it is actually 2M of unified cache for both cores according to Intel's docs/marketing for the Yonahs. The 1M+1M spec on some vendor pages (such as NewEgg) might be a holdover from the Athlon 64 X2 (which has independent L2 caches) and the Pentium D (which also appears to have independent L2 caches).

      That unified cache between the cores could provide a significant performance boost that would make up for the unpleasant shared FSB.

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      retrorocket.o not found, launch anyway?
    4. Re:What's new? by Anonymous+Freak · · Score: 1
      Yonah supposedly also includes virtualization support. (It was supposed to, I haven't seen any confirmation either way whether or not it actually is in there. Anyone know if it would show in /proc/cpuinfo and what specific flags I should look for? I've got a T2500-based laptop in the other room.)


      Yes, Core Duo has Virtualization. Take a peek at Intel's Performance Brief, or a Press Release.

      Also I have not seen any confirmation yet that the new Sossaman actuall supports multiple CPU packages per system. Intel's comparison page for the Xeons lists all of the Xeons I've tried as being MP capable, while the new Xeon LVs are only listed with a system type of "DP" - the die/package already HAS two processors though.


      Take a peek at Intel's Advanced Platform Technologies document. In it, it mentions dual, dual-core Xeon LV 2.0 GHz processors.

      As to the issue of shared vs. independent cache between the cores - yes, it looks like while most third-party specs for the Yonah list it as "1M + 1M", it is actually 2M of unified cache for both cores according to Intel's docs/marketing for the Yonahs. The 1M+1M spec on some vendor pages (such as NewEgg) might be a holdover from the Athlon 64 X2 (which has independent L2 caches) and the Pentium D (which also appears to have independent L2 caches).


      Indeed, both Athlon X2 and Pentium D use separate L2 caches per core. Yonah and Sossaman use a single dual-ported L2 cache. 1M+1M is likely either vendor confusion, or just trying to be clear, if technically incorrect.

      That unified cache between the cores could provide a significant performance boost that would make up for the unpleasant shared FSB.


      A shared cache will cut down on FSB hits significantly in high-cache-hit circumstances between processors. In the Pentium D, for example, if one core has a piece of data in its cache, and the other core wants that data, well, it has to go to main memory for it, since the two cores aren't aware of what is in each other's cache. On Athlon X2, it's a little better. The two are aware of what are in each other's caches, but must go through the HyperTransport bus (same as to chipset) to get it. At least on Athlon, the memory bus controller is shared between cores, so that the two cores don't have to fight each other for main memory access. (Athlon X2 behaves to main memory similarly to the way Yonah/Sossaman does to L2.)

      Unfortunately, it appears that Sossaman still has a shared FSB between sockets and cores. That means effectively 4 processors on the single 667 MHz bus. Intel has hinted that Woodcrest will use separate links to each socket, a la PowerPC 970 and Opteron. That will be a welcome change.

      (And I wonder with Intel's push for 4-core and 8+core systems in the coming years... Will they significantly increase the front side bus to the socket, or will each socket start to contain multiple FSB links? I mean, even if you've got a full-speed bus, a single 3 GHz bus for an 8-core 3 GHz chip won't be fast enough to keep those cores fed.)
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    5. Re:What's new? by jdb8167 · · Score: 4, Informative

      Two things, SMP and a 34-bit address bus for up to 16GB of RAM.

  9. Dual processor configurations by NekoXP · · Score: 2, Informative

    Xeon LV supports SMP.. I think that is the only difference.

    Now it's been released I wonder if Apple are going to put out a PowerMac based on it..

    1. Re:Dual processor configurations by Jeff+DeMaagd · · Score: 2, Informative

      I wouldn't expect it to be PowerMac material. Code name Woodcrest is a better fit. It seems to clock a lot better (up to 3GHz, with a decent CPI to boot) with better cache (4MB per chip) and a better front side bus, up to 1333 MHz and support 64 bit instructions.

    2. Re:Dual processor configurations by NekoXP · · Score: 1

      XServe then?

      It has potential for a serious budget offering. Perhaps a cheap Apple workstation for once..

    3. Re:Dual processor configurations by antime · · Score: 1

      I don't think Apple's "pro" market would would be satisfied with a machine limited to 2GB of memory (which seems to be the limit of OSX on 32-bit hardware).

    4. Re:Dual processor configurations by NekoXP · · Score: 1

      Most people I know with a Quad G5 only throw 2GB into it anyway. Much more is prohibitively expensive right now, specially on top of a $3000 box, and really 2GB is still a lot of memory to throw at a machine these days. I think I know a guy with a dual G5 and he put 2.5GB into it for some reason (seems an odd value to me).

      The lower end PowerMac models have always had a lower memory limit than the top end models. I recall it being 3GB and 8GB at one time, maybe nowadays it is all 16GB? But it was used to differentiate between models. I don't think Apple have any scruples against it (it is after all the same northbridges in the entire range, the limit is actually down to something innocuous like firmware)

    5. Re:Dual processor configurations by mrchaotica · · Score: 1
      I think I know a guy with a dual G5 and he put 2.5GB into it for some reason (seems an odd value to me).
      2GB aftermarket plus the 512MB it came with. He just didn't want to throw away the original 512MB, that's all.
      --

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  10. They have done this over and over. by cyberlotnet · · Score: 1

    All those complaining about the shared cache and low bus speed have to remember, Intel has a history of "crutching" new processors to ensure they don't kill the sale of there old processors.

    Until they kill the current xeon line and get rid of the inventory on stock they will keep this chip under a tight noose, only ramping it up as they feel the need.

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  11. Yes but... by GimliGloin · · Score: 1

    Why didn't THIS go into the Mac-Mini?? I am outraged!!!

    GSG

  12. Re:A start, but no 64-bit? 667 Mhz front-side bus? by gnuadam · · Score: 2, Interesting

    Alternately, apple put pressure for a chip that they can use to put in a new "core quad" (ie 2 of these) power mac to be announced 1 Apr? Timing's right ... (intel announces this 2 weeks before 1 Apr) ... Hmmmmm. At least this quad monster won't have to be water cooled.

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  13. Re:A start, but no 64-bit? 667 Mhz front-side bus? by IntlHarvester · · Score: 1

    Re: 667 Mhz bus

    These are low-power chips that are based on the laptop models. The real "Core" Xeons are coming in a few months and will have a bus at double that (IIRC).

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  14. Re:A start, but no 64-bit? 667 Mhz front-side bus? by Anonymous Coward · · Score: 0
    This is just a stepping stone. See the recent article in Real World Tech for lots of details on Intel's upcoming server chips. This 32-bit model is just a quickie model (it's just the new laptop design packaged for the blade-server market): the REAL fun models are coming in a few months.

    I've actually been accused of being a bit of an AMD fan boy myself, but the upcoming Intel chips are no joke either. It really looks like they've almost fully recovered from the Netburst mis-step. The race is back on.

  15. Re:A start, but no 64-bit? 667 Mhz front-side bus? by vought · · Score: 1

    Oh God, I hope Apple doesn't use these chips....

  16. Re:A start, but no 64-bit? 667 Mhz front-side bus? by Burning1 · · Score: 2, Funny

    "Intel's going to have to do a lot more than this to catch up to AMD in the server space."

    Back in 2001 when I was just an AMD fanboy I would have made a mess in my pants upon hearing that.

  17. No words needed. by Anonymous Coward · · Score: 1, Informative

    Dual Dual-Core Opterons vs Xeon (Paxville)

    1. Re:No words needed. by Anonymous Coward · · Score: 0

      Right, excepted that those Xeons are not the ones in TFA

  18. I don't mean to ponfificate, but by xactuary · · Score: 2, Funny
    Didn't Pope Zeon LV kiss the tarmac at Starfleet Academy?

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  19. 4 times shit is still shit by Chicken04GTO · · Score: 1

    "The new chip has "four times the performance-per-Watt of its existing 2.8GHz LV Xeon CPU"" 4 times shit is still shit