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A Greener Chip Manufacturing Process
gardenermike writes "A new chip manufacturing process has been developed which uses UV light instead of high temperatures to prepare the silicon. This could lead to cheaper chips and greener factories if it pans out. Apparently the main problem is defects in the material, which are currently 'ironed out' as a side-effect of the extreme temperatures used."
I'd hardly call it a side-effect to have a process that minimizes defects. I'd rather call that an essential-effect.
"It's the height of ridiculousness to say for those 9 lines you get hundreds of millions."
Silicon dioxide is the all purpose dielectric in most current chips. It is slowly and painfully being replaced by "low K" materials between wires and "high K" materials under the gate electrodes. The transition to Low K/High K has been pushed out again and again but it is being used in some chips now. If the this new method of growing silicon dioxide is still in research, it seems doomed to reach production shortly after it is no longer needed.
Would this process also be useful for making silicon based solar cells? Or is it at a step of silicon processing that's too far towards chip specific manufacturing? If solar cells can be made more cheaply, I wonder what this could make the initial $/watt investment.
"Common sense will be the death of us all"
Good thing this is Slashdot, I usually throw the green chips away.
Wanna fight ? Bend over, stick your head up your ass, and fight for air.
Semi-arbitrary. Each whole generation is half the feature size of the generation before, starting from 0.650 micron (650nm). In between are "half" generations counting down from 1000micron.
Half generations: 1000, 500, 250, 130, 65, 32, 16
Whole generations: 650, 350, 180, 90, 45, 22
The precise digits are chosen for convenience and actual processes vary a bit up and down for a given technology node. Each node requires new equipment. By moving from node to node together, manufacturers share some of the cost of development. Still, odd ball nodes do exist. DRAM's are often manufactured at intermediate dimentions and 150nm is used by some foundaries.
Many fabless chip makers will skip half generations. I know a lot of manufacturers went straight from 350 to 180. Still, the choice to skip or not is mostly economic. If a node lands durring a recession, fabless chip makers are likely to hold off until the node that follows. The fabs don't really have a choice. They have to produce each generation in sequence, at least at small scale, or they will not have the technological base to start work on the nodes that follow.
The sizes are governed by 2 factors, the wavelength of the UV light used, currently 193nm, transitioning to the 157nm for the 45nm chips, and the diffraction gratings/refraction of immersion fluid/polarization of said fluid, etc. used. Due to the physics behind this (i wont bore you with the long equations, because i dont want to do them again) there's basically certain points at which these effects add up to the greatest possible resolution/intensity/etc. Any more in depth and i'd have to dig up my lithography text, and i dont really want to :)
drunk chemists
Firstly, I have to say that, what they claim to serve as a >novel> technique is not completely novel. Of course, it was known that SiO2 could be formed by other means then sintering ( heating the silicon and letting the oxygen atoms dissolve in silicon ) but the problem has always been the purity.
Semiconductors, especially devices in nanometer scaling need to be extremely pure. Their lattice structure -hence their electrical effects- can easily be distorted or failed by very little deviations, say, in dopant concentrations random dopant fluctuations. This is shortly called , RDF.
RDF has become a major concern especially for the newcoming generations because basically when you scale down the channel length, the channel lengths are becoming so narrow (and small) that only about 100 hundred dopant atoms fall inside the channel volume. This , obviously, increases the sensitivity and failure rate of these transistors, let alone their variations (like threshold voltages) in a single die.
From a mass production point of view, we want to get as uniform parameters as we can from a complete die. The ratio of successful ( uniform and working ) transistors to the total die area divided by a single transistor area ( which means the total number of transistors we wanted to harvest from that die ) gives us the `yield`.
Now, taking into account the fact that even a failure of a single transistor, could lead to the failure of an entire word line of an SRAM , the yield strongly influences the SRAM or chip reliability.
And for the companies, it does not matter whether you prepare the chip at room temperature but in a more sloppy way, because ultimately it is going to cost more !
Of course the need for extreme purity in nanoscale devices is not realized completely. The reason is that we have not produced those chips yet. However, these issues ( especially RDF and process variations- you can google these and see yourself) are very hot topics in LOW POWER VLSI design.
The people who work in these fields are surely aware of the need for an accurate fabrication and will just ignore this kind of work. There are some papers that try to reduce these effects only to succeed in a relatively low way.
In modern research, you can easily publish a paper by changing the slightest detail of a published paper or you can slightly vary this known application and claim that you have come up with a totally novel ida.
This is a draw-back.
In short, they are not going to make anything green, UNLESS of course, they find a better and reliable method satisfying the needs of the upcoming nanoscale devices.
Then I would shut up
There's plenty of room at the bottom! Richard P. Feynmann