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A Greener Chip Manufacturing Process
gardenermike writes "A new chip manufacturing process has been developed which uses UV light instead of high temperatures to prepare the silicon. This could lead to cheaper chips and greener factories if it pans out. Apparently the main problem is defects in the material, which are currently 'ironed out' as a side-effect of the extreme temperatures used."
I'd hardly call it a side-effect to have a process that minimizes defects. I'd rather call that an essential-effect.
"It's the height of ridiculousness to say for those 9 lines you get hundreds of millions."
Silicon dioxide is the all purpose dielectric in most current chips. It is slowly and painfully being replaced by "low K" materials between wires and "high K" materials under the gate electrodes. The transition to Low K/High K has been pushed out again and again but it is being used in some chips now. If the this new method of growing silicon dioxide is still in research, it seems doomed to reach production shortly after it is no longer needed.
Would this process also be useful for making silicon based solar cells? Or is it at a step of silicon processing that's too far towards chip specific manufacturing? If solar cells can be made more cheaply, I wonder what this could make the initial $/watt investment.
"Common sense will be the death of us all"
Good thing this is Slashdot, I usually throw the green chips away.
Wanna fight ? Bend over, stick your head up your ass, and fight for air.
I posted this to an earlier discussion, where it seems to be eliciting no replies, so I'll ask again here. The Wikipedia entry states: "The successors to 45nm technology will be 32 nm, 22 nm, and then 16 nm technology; it is possible that these numbers are arbitrary, but it is also possible that they reflect fundamental physical limits of some sort." So which is it, arbitrary or fundamental physical limits?
And now, a PSA from David Lynch.
let see
you compute probably uses around 1KWh every6 hours.(probably more like 4 hours)
let's se you pay12cents a KWh
thats 48 cents a day. about 15 bucks a month.
figure half of that is the amount of time that you would be using the computer anyway.
extra 7.5 bucks a month.
If you use AC, then it costs you even more.
The Kruger Dunning explains most post on
Firstly, I have to say that, what they claim to serve as a >novel> technique is not completely novel. Of course, it was known that SiO2 could be formed by other means then sintering ( heating the silicon and letting the oxygen atoms dissolve in silicon ) but the problem has always been the purity.
Semiconductors, especially devices in nanometer scaling need to be extremely pure. Their lattice structure -hence their electrical effects- can easily be distorted or failed by very little deviations, say, in dopant concentrations random dopant fluctuations. This is shortly called , RDF.
RDF has become a major concern especially for the newcoming generations because basically when you scale down the channel length, the channel lengths are becoming so narrow (and small) that only about 100 hundred dopant atoms fall inside the channel volume. This , obviously, increases the sensitivity and failure rate of these transistors, let alone their variations (like threshold voltages) in a single die.
From a mass production point of view, we want to get as uniform parameters as we can from a complete die. The ratio of successful ( uniform and working ) transistors to the total die area divided by a single transistor area ( which means the total number of transistors we wanted to harvest from that die ) gives us the `yield`.
Now, taking into account the fact that even a failure of a single transistor, could lead to the failure of an entire word line of an SRAM , the yield strongly influences the SRAM or chip reliability.
And for the companies, it does not matter whether you prepare the chip at room temperature but in a more sloppy way, because ultimately it is going to cost more !
Of course the need for extreme purity in nanoscale devices is not realized completely. The reason is that we have not produced those chips yet. However, these issues ( especially RDF and process variations- you can google these and see yourself) are very hot topics in LOW POWER VLSI design.
The people who work in these fields are surely aware of the need for an accurate fabrication and will just ignore this kind of work. There are some papers that try to reduce these effects only to succeed in a relatively low way.
In modern research, you can easily publish a paper by changing the slightest detail of a published paper or you can slightly vary this known application and claim that you have come up with a totally novel ida.
This is a draw-back.
In short, they are not going to make anything green, UNLESS of course, they find a better and reliable method satisfying the needs of the upcoming nanoscale devices.
Then I would shut up
There's plenty of room at the bottom! Richard P. Feynmann