Slashdot Mirror
Could HP Beat Moore's Law?
John H. Doe writes "A number type of nano-scale architecture developed in the research labs of Hewlett-Packard could beat Moore's Law and advance the progress of of microprocessor development three generations in one hit. The new architecture uses a design technique that will enable chip makers to pack eight times as many transistors as is currently possible on a standard 45nm field programmable gate array (FPGA) chip.""
In Soviet Russia, dots slash you!
It's a prediction and actually a self-fulfilling one, to some degree. In fact, it's as much, or more, about economics than technology. If you look, the original wording even states "cost". Upgrade too fast and you'll go broke because people won't upgrade with you that fast (they'll start skipping 'generations' in their upgrades).
Xilinx is the worlds largest producer of FPGAs.
Their biggest customer? Cisco. (by far)
The big iron routing guys use heaps in high end devices.
--Q
The mean value theorem shows that if the average rate is x, and the instantaneous rate ever goes below x, then it must necessarily also be above x sometimes. Put another way, progress will sometimes be faster than other times.
Dewey, what part of this looks like authorities should be involved?
Anyone who wants a low-volume run of custom chips. For runs up to a few thousand, FPGAs are cheaper than ASICs (and have the advantage of being firmware-upgradable). If you don't need latest-process speed or power efficiency then FPGAs are likely to be good enough. Take a look here for some of the people who use them.
I am TheRaven on Soylent News
Yes, actually. BTW, am I the only one who thinks it darn cool that the SaarCor team does their work in JHDL rather than VHDL or (ugh) Verilog? I wonder if the RPU is also JHDL?
Javascript + Nintendo DSi = DSiCade
Hi, I work as field apps for a large FPGA manufacturer. The interconnect lengths count for a large proportion of the delay between each configurable logic cell (LE in our terminology), so a shortening in interconnect is not only useful from a transistor count view, but also an upper performance limit view. As for the first poster the larget current FPGA's (Altera's StratixIII, Xilinx Virtex 5 series) have multiple millions (sorry can't be bothered to look up the exact figures) of transistors. However, the flexibility of an FPGA is not that it can just be configured like a Microprocessor (though it can, see Altera's NIOSII) but to act like almost any digital logic you wish to conceive of. Want a FFT function? Don't write it in C/C++, describe it in hardware - much much faster than code, and getting on for an order of magnitude or more faster than on current DSP chips. To do the this, the simplest architecture element is a Logic Element (in Altera technology at least) - this usually (but not always, different vendors have their own twist on these) consists of a 4 input look up table and an associated programmable logic register. Combining a number of these LE's through the routing can create sequential or purely combinatorial logic functions. On top of this many hardware vedors also include special blocks for on chip RAM or ROM, and commonly now DSP multipliers. Of coures, RAM/ROM and muolts can theoratically also be built from discrete LE's but this can be inefficient so dedicated blocks are used. The latest Altera StratixIII family uses ALM (Arithmetic Logic Units) which are slightly larger than an LE but allow more functions to be implemented in one ALM than an LE, potentially reducing the number of logic levels to privide any given funtion, and in turn this can increase system througput and therefore performance. The current larget FPGA announce is the StratixIII EP3S340, which contains 340K equivalent LE's or if you prefer 340K programmable registers (for simplicity). You should ignore exact gate count comparisons between vendors as these are usually marketing figures. Some will include the gates used to configure the FPGA as well as usable ones accessible for use as general logic funtions, so can skew the figures somewhat.
You are seriously behind the times, my friend. Xilinx's smallest offerings provide ~20,000 gates, while their largest offerings offer millions of gates placed on a chip of over 1.1 billion transistors.
22K transistors is solidly inside CPLD territory these days.
Javascript + Nintendo DSi = DSiCade
FPGAs are not microcontrollers. They are programmable logic devices. You can use an FPGA to implement a microcontroller, a microprocessor, or any other logic device.
You probably wouldn't be able to put the latest Xeon processor on an FPGA, but to say that they are far slower and smaller than modern processors is incaccurate. There are plenty of FPGAs that can handle signals in excess of 1GHz, and a 22,000 transistor FPGA is a VERY small FPGA.
Many custom chips including custom processors are first developed and tested on FPGAs before they become ASICs. In fact, you can give your FPGA design files to an IBM or a TI, and they'll gladly turn it into an ASIC for you -- for a fee. Often times, FPGAs are used in designs without ever going to an ASIC. Generally, the only reason you build an ASIC is because the per chip cost is much cheaper. Heat and performance are usually secondary considderations. There is, however, a big up front cost to doing an ASIC, so for low volume parts or designs that might need to be upgraded or fixed later, FPGAs are generally the better option.
There's also a middle ground -- so called "hard copy" FPGAs. This is when you give your design files to Xilinx or Altera with a big check, and they sell you special FPGAs that are guaranteed to work with your design (but not necessarily other designs). In exchange, you get the chips a lot cheaper and they can also disable parts of the chip your design doesn't use to reduce power consumption. The FPGA manufacturers benefit by being able to sell chips that would otherwise be defective but are suitable for certain designs.
No true ... because of timing requirements ... if one gate is used it may rule out using others because of how the gates are connected ... i.e. picking one gate and 1 route may not allow certain gates to be connected ... so the 6 to 1 ratio refers to "wasted gates" ... I believe. This is because all gates are not all directly connected to each other ...
If this new technology allows more routes ... i believe you will get less gate waste ...
I am just a software dev ... so i could be wrong though ... but this is my understanding ...
No. Contrary to popular belief, ASICs don't utilize all of the gates they have either. There are limitations (even more so) in ASIC-land where you only have so many metal layers on top of your silicon to route your interconnects. Granted, a human being laying it out by hand is much better than an auto-router, but there will still be waste. The same is true of an FPGA and the general rule is that you never utilize more than 70-80% of your available logic resources. This way, there is some flexibility the auto-router has when placing and routing your logic.
The 80-90% number that the article mentions is in absolute gate number (not equivalent gate-number that your custom logic running on the FPGA would use). So basically, if you design a 4-bit counter that requires, let's say, 20 gates. An FPGA will need roughly 200 real gates (each gate requiring certain number of transistors) to simulate this because it must be able to not only simulate that 4-bit counter but a large set of combinations of interconnecting those 20 gates.
This would take that routing network that is currently done by transistors, and move it into the interconnect. This is an interesting move in that it is the first (IIRC) time that interconnects have been used to perform logic (which is really what a switch fabric is) rather than to simply connect logic. An interesting side-note is that back in college, I had a professor researching into using interconnects (wires) alone to do logical operations without transistors at all. I wonder how that's going.