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Could HP Beat Moore's Law?
John H. Doe writes "A number type of nano-scale architecture developed in the research labs of Hewlett-Packard could beat Moore's Law and advance the progress of of microprocessor development three generations in one hit. The new architecture uses a design technique that will enable chip makers to pack eight times as many transistors as is currently possible on a standard 45nm field programmable gate array (FPGA) chip.""
Since the wiring in an FPGA is not fixed, they have to integrate more flexible ways of routing. According to TFA this takes up 80% to 90% of the silicon, leading to a much worse ratio of wiring to transistors dedicated to logic processing compared to "normal" chips. HP is developing something they call "field programmable nanowire interconnect (FPNI)", which consumes a lot less space. So they are not beating Moore's law, they improve chip space use in FPGAs to become similar to what todays dies with fixed routing achieve.
And even if you are desperately seeking more efficient FPGA, you'd have to be patient. TFA mentions that they are targeting a 25-fold increase packing density compared to todays 45nm chips in 2020. That's thirteen years, which in Moore's laws steps means about eight 18 month periods, each doubling density. My math may be flawed, but shouldn't that mean that by then we have 2^8 = 256 times the density in the normal process as we have today?
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I never understood why it was called a law. It was an incredibly accurate prediction, but there was nothing holding is there. I would think that any dramatic increase in technoloby would lead to a jump larger than Moore's law.
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Moore's "Law" is actually a prediction that's been remarkably accurate.
I think, though, that's what happening here is employing the technology is causing positive feedback loops in the design and development of the technology, which is accelerating the improvement of the technology.
It's only going to get faster from here. Human consciousness executing on "silicon" by 2030.
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As a rule of thumb i was told ... an fpga normally uses 6 gates to 1 gate used by a custom ASIC chip ... so a 5 million gate chip would require a FPGA with 30 million gates ...
This may have changed over the years ... but i'd like to know how this announcement changes this heuristic ...
HP Engineers Defy Moore's Law, New Nano-Chip Prototype in 2008
They havent even made a chip yet.
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OK, the actual paper's here (full text freely available).
As far as I can tell this has nothing to do with standard processors and everything to do with FPGAs.
It seems what they propose is: Instead of the FPGA configuration bits being done with gates on the silicon wafer, why not perform configuration by configuring the metal-to-metal interconnects? After all, if the metal layers are thick compared to the interconnects between them, you can blow connections you don't need like blowing a fuse. By removing the FPGA configuration bits from the silicon wafer, they can save a lot of space, leading to higher speeds and lower costs.
They have a clever way of arranging such a system, which should be easy to fabricate.
What Moore's law is supposed to have to do with this I don't know.
Michael
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I thought FPGA's were a common microcontroller that *could* be altered to run as a microprocessor. You can configure FPGA's to run as a micro-controller and you can get microprocessors to act like a microcontroller but they are not the same thing. Most FPGA's run at far lower clock frequencies and far lower transistor density's when compared to your desktop CPU. This isn't because one is better than the other its because they are designed for different purposes, getting more transistors on a chip is great for your smartphone but doesn't mean much for your desktop.
I just don't see how this would would allow for moore's law to be broken. The largest FPGA I have been taught about (and gotten to use) had 22,000 transistors on it, I thought your average CPU was supposed to have billions.
there are lots of uses for FPGAs in radar processing, image recognition, you can even do small
floating point kernels REALLY fast on FPGAs if done correctly.
granted on most of them you have to know verilog or vhdl to use them, but there are a couple
companies that have fully functional C/Fortran programming environments that take it all
the way down onto an FPGA. using those general codes can run faster on FPGAs.
plus they are really low power. a room full of general computers running a teraflop
takes large amounts of power, fpga based systems take 1/20th or so the watts.
If I could walk that way I wouldnt need cologne.
So they are not beating Moore's law, they improve chip space use in FPGAs to become similar to what todays dies with fixed routing achieve
Agreed, but if the article were titled "HP Enables Increase in FPGA Logic Density", it would have never made it to a slashdot headline.
Roughly, other advancements... multi-cores etc. We should keep pace with Moore's law. It is a rather stupid suggestion. Every time one of these stories comes along they always suggest they are beating Moore's law, when really they keep pace.
New Wammy Co. method for silicon fab... this is going to double the speed of our computers and crush Moore's Law! It should be on the market about 18 months from now!
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