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DRAM Almost as Fast as SRAM
An anonymous reader writes "IBM said it has been able to speed up the DRAM to the point where it's nearly as fast as SRAM, and that the result is a type of memory known as embedded DRAM, or eDRAM, that helps boost the performance of chips with multiple core calculating engines and is particularly suited for enabling the movement of graphics in gaming and other multimedia applications. DRAM will also continue to be used off the chip."
to go for title of most patents filed in 2007
"Stallman says add to this code and you are one of us. Gates says use this code and you belong to us."
With all these improvements in processor and RAM speed, when can I expect a faster HDD? A solid state drive would be nice.
All chips wait at the same speed. Why not concentrate on the bottlenecks rather than what is already one of the fastest components in any system.
There is no "I disagree" mod for a reason. Flamebait, Troll, and Overrated are not substitutes.
To those wondering why it would be good to have DRAM as fast as SRAM: SRAM doesn't need to be "refreshed" constantly, and is faster, but takes up many more transistors and is therefore much less dense and more expensive for the same amount of memory.
However with DRAM it takes quite a bit of power just to keep data in memory (because of the constant "refreshes"), which isn't the case with SRAM. So this discovery wouldn't take SRAM out of production for applications which require its low power usage.
// MD_Update(&m,buf,j);
I don't get why this is news. Embedded-DRAM has been in heavy usage for many years now.
Both the title and the summary are quite misleading, since eDRAM is on-chip and that of course is much faster than external off-chip memory, be SRAM, DRAM or whatever.
Some big examples? PS2, Nintendo Gamecube, Wii, Xbox 360. All these consoles use eDRAM for their GPU's on-chip framebuffers to enhance their performance, and that goes back to at least the year 2000 when the PS2 came out.
Some will be quick to say "no, the Nintendo consoles use 1T-SRAM, not DRAM". Yeah, right, but even 1T-SRAM (despite its name) is a form of embedded-DRAM.
- Otaku no naka no otaku, otaking da!!!
If you could stick a crapload of this on the Cell, then those SPEs could have more than 256kB memory each, and utilizing them would become dramatically easier.
I'd guess the next revision of Cell will have a shitload of eDRAM on it. And it will either have more SPEs, or a new bus that allows multiple Cells to be used. The latter would be more expensive to implement, but probably result in higher yields than substantially growing the Cell to support more coprocessors - the yields are already poor if they just turn all the SPEs on, or else why would they be disabling one?
"You're right," Fisheye says. "I should have set it on 'whip' or 'chop.'"
EE Times article. Today SRAM is used for processor caches, but new multicore chips need massive (i.e. expensive) cache. Because eDRAM is much denser than SRAM, it allows chip designers to fit much more cache in the same size chip, increasing overall performance. IBM and AMD use silicon-on-insulator (SOI) technology, while the rest of the industry uses bulk CMOS; eDRAM for bulk has been available for a while (it's used in Xbox 360 and BlueGene/L for example), but now IBM has developed SOI eDRAM that can be used in IBM's future processors (and maybe AMD's).
There are 2 areas of latency for a cache, the first is the performance of the actual data cells, and the second is the speed of doing a lookup in the cache. The larger the cache, and the higher the degree of set associativity, the longer the lookup takes. Thus you're unlikely to see this eDRAM used for L1 caches, and probably not for L2 caches either, as more cache would slow them down, even if the cells are just as fast as SRAM. The sweet spot will probably be for L3 caches, that are already slow by cache standards, but a whole lot faster than system memory. Since L3 caches are large, the cost savings for switching to eDRAM would be largest there.
As for power concerns, DRAM is higher than SRAM, but a larger L3 cache may reduce the traffic through the memory controller, and out to the DIMMs, which will probably more than make up for any increase in power density in the cache.
No, I'm not a fan of patent trolls; but this isn't patent trolling. IBM has created a new, better way to embed cache RAM on the CPU die, at a signifigant cost in both manpower and materiel. This isn't like they patented "a method to check customers out with one click" or something similarly banal. This is a real, new technology which took a great deal of time, energy and work to create. No "prior art", no "trivially obvious" - this is exactly the kind of technological advancement which patents should protect.
I am in no way an expert, but I read about other upcoming types of RAM which also sound interesting:
Z-RAM. One cell is a single transistor. Faster than SRAM, which uses 6 transistors per cell. http://en.wikipedia.org/wiki/ZRAM
TTRAM. One cell contains 2 transistors. As fast as SRAM, according to Wikipedia. http://en.wikipedia.org/wiki/TTRAM
If you've plenty of memory on-die the bus becomes irrelevant ;) That's how Intel is keeping up with AMD - big cache band-aid on the slow FSB so they can compete with HT.
Intel transfer the difficult from Hadware to software, for get more power, programmer need more technology. -- chinaitn