IBM Heralds 3-D Chip Breakthrough

David Kesmodel from WSJ writes to let us know about an IBM breakthrough: a practical three-dimensional semiconductor chip that can be stacked on top of another electronic device in a vertical configuration. Chip makers have worked for years to develop ways to connect one type of chip to another vertically to reduce size and power use. The IBM technique of "through-silicon vias" offers a thousand-fold reduction in connector length and a hundred-fold increase in connector density. The new chips may appear in cellphones and other communication devices as soon as next year. PhysOrg has more details.

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More information

[karvind]

As article says they had been working on it for a long time, they had published few details before.

http://www.research.ibm.com/journal/rd/504/topol.h tml

http://domino.watson.ibm.com/comm/pr.nsf/pages/new s.20021111_3d_ic.html

Well

[ShooterNeo]

This is it. Maybe. Possibly major problems with heat dissipation. However, there are some massive advantages :

1. One tradeoff IC designers always face is that the fastest, lowest latency access is always to on-die components. On-Die memory (cache) is almost ALWAYS faster, coprocessor interconnects (like for dual core) are far quicker, ect. With any given level of state of the art, you can get a much higher clock signal over itsy bitty paths on silicon from one side of the chip to the other than going out to big, clunky, exremely long wires.

2. The tradeoff is that a bigger chip radically reduces yields : the chance of a defect causing a chip to be bad goes up with the square of the number of gates.

3. This technology allows one to use multiple dies, and to interconnect them later. There's just one problem.

HEAT DISSIPATION. A 3d chip will of course have it's heating per square centimeter multiplied by the number of layers. The obvious solution, internal heatpipes, has not yet been shown to be manufacturable.

Hence TFA mentioning use in devices such as cell phones, where bleeding edge high wattage performance is not a factor.

Re:Well

[drinkypoo]

HEAT DISSIPATION. A 3d chip will of course have it's heating per square centimeter multiplied by the number of layers. The obvious solution, internal heatpipes, has not yet been shown to be manufacturable. Hence TFA mentioning use in devices such as cell phones, where bleeding edge high wattage performance is not a factor.

It's useful in other spaces, too. If you have a massively parallelizable task, then you could use this technology to have a stack of CPUs in less space on the board, which would reduce the cost of the system. You could run at low clock rates with huge numbers of processes and/or threads.

Re:What??????

[stevesliva]

The chips didn't exist as 3-D objects prior to this? Infact, wouldn't a chip that only exists in two dimensions be much more difficult to make?

One layer of silicon substrate, followed by many layers of polysilicon and wires and insulator. There is as of yet no practical way to fabricate to transistors on top of each other on a wafer. It's always the transistor on bottom, wiring on top. The transistors themselves are only a 2D array (but yes they are 3D devices). Sounds like this technique bores holes through the silicon substrate to make contact with another wafer below, so you could conceivably have transistors above and below.

Re:Very nice, but...

[MightyYar]

They already do that, too. Stacked die are not new - this is simply a way to connect them without using a wire bonder or flip-chip. One of the traditional problems in wirebonder-less solutions is that you then have to match up the die with the substrate - this means that a simple silicon die shrink also requires a substrate re-design.

I think that this sounds like a relatively expensive process, but it should enable a thinner profile than flip-chip or wirebonding.

Re:Very nice, but...

[MightyYar]

Die shrinks happen way to quickly to establish standards. Most manufacturers don't even try to match up substrates with chips - they just use a wire bonder. Only packages with specialized requirements keep the substrate and chip matched up so that they can use flip-chip or some other interconnect process... inkjet heads still use tab bonding, for instance.

Re:Heat

[MightyYar]

I don't know much about the cooling issues, but I know that they back-grind the chips to make them thinner. For instance, if they are replacing a memory package that used to consist of 1 chip with 3 stacked chips, they will grind the 3 stacked chips so that they are no taller overall than the 1 chip. Typical silicon thicknesses used to be 14-20 mils (355 - 500 microns). Now we are seeing as thin as 3 mils (75 microns), with folks at trade shows demonstrating even thinner.

Don't ask me why people still use mils in the packaging industry... they just do. It makes for some weird units, like g/mil^2. Yuck.

Re:I wonder how they will cool this?

[SQL Error]

You wouldn't be able to stack multiple desktop CPUs, because it would generate too much heat. But you could stack a CPU on top of its own level 2 cache instead of next to it, making for shorter wires and a faster chip. Or stack a GPU on top of DRAM, so that you could have a 2048-bit bus instead of 256-bit.

Then they just rely on the upper layer to conduct enough heat to keep the low layers cool.

Re:I wonder how they will cool this?

[duncanFrance]

There are some thermal advantages to this sort of interconnect. Since it keeps the wirelength short it means the drivers don't have to be so powerful. Hence a fair amount less heat will be generated. Driving any amount of capacitance at GHz speeds wastes shed-loads of power.

Average power dissipated = V*V * f * C

So reducing V obviously makes a big difference (hence partly why operating voltages of ICs decrease with frequency), but getting C down will help also.

Re:No more planar graphs!

[RuleBritannia]

You appear to be under the misapprehension that VLSI designs are planar graphs. The place and route tools used to move from RTL to GDSII layouts make assumptions (depending upon the manufacturing process) of anywhere between 4 and 20 metal layers.

The technology described in the article is exciting but not novel... academics has been exploring memory hierachies, hardware dynamic thread scheduling, and introspective debug solutions for some years.

For reference... Last years ASPLOS (06) conference includes 2 papers with disruptive 3D stacking technologies.

PICOSERVER: USING 3D STACKING TECHNOLOGY TO ENABLE A COMPACT ENERGY EFFICIENT CHIP MULTIPROCESSOR.
Joint paper between Univ. of Mich. and ARM which shows how 3D stacking of DRAM dies (which have difference process req. to logic)on top of logic can radically reduce power, increase memory bandwidth and save area (since L2 cache becomes unnecessary)

INTROSPECTIVE 3D CHIPS.
UC Santa Barbara group show that 3D stacking allows the inclusion of a host of dynamic debug features which allow monitoring of the processor pipeline - without adding cost to the production version of the chip.

So... not just cool, super cool , but fundamental challenges remain, chiefly - can we achieve reliable interconnects between thousands of die-to-die vias (with the implication that if you bugger it up, both dies are useless), secondly, can we develop better wafer level testing so we don't end up going through the expensive stacking process with duff dies. Thirdly, better tools for modelling heat dissipation in such stacks is needed if they are going to be reliable in every-day use.

Kind Regards