AMD Releases Image of Phenom/Barcelona Die
MojoKid writes "A few weeks ago, AMD
released information on new branding for their desktop derivatives of the Barcelona core, now dubbed the Phenom FX, X4 and X2. If you're unfamiliar with Phenom, the processors will be based on AMD's K10 architecture. They've been tight lipped about specifics, but we know that it will feature a faster on-die memory controller, support 64-bit and 128-bit SSE operations, and they'll be outfitted with 2MB of on-chip L2 cache (512KB dedicated per core) in addition to 2MB of shared L3 cache. This week, instead of revealing some more of the juicy details regarding those enhancements, AMD just sent over a tasty photo of a Phenom die. At least it's something."
can you see how fast it is? How about some specs we understand?
I know that this is just a ploy to build up hype for the new processors... I just hope that the processor performs up to expectations.
AMD really needs to respond to the Core 2 Duo's with something that tells the world that they are still in the race. I really don't want to see Intel become the unchallenged winner of the silicon wars... it would hurt us users in the long run.
I fear that it is a real possibility however. The cost of fabs, R&D, and marketing have grown so much in the last few years that it would be VERY difficult for any newcomer to compete with Intel unless they managed to develop a completely different and low cost way to manufacture their chips... or they are very heavily backed.
Sometimes the best solution is to stop wasting time looking for an easy solution.
On-chip connectivity can be much broader and lower-latency than off-chip connectivity. The two-dual-core in one package "quad cores" of Intel have to talk via the off-package north bridge. As you can see from the AMD Barcelona/K10/10h snapshot, the cores live together on a single piece of silicon.
The space between the the cores is a very broad crossbar, allowing fast inter-core synchronization/cache-coherency. The uniform block at the edge of the chip, outside the cores, is the L3 cache shared by all four cores. Each core has its own L1 and L2 cache. This design is nicely symmetric: each core has equivalent resources. It should do very well on heavy-duty symmetric multiprocessing applications.
And it will probably require ANOTHER slot type and force me to upgrade my motherboard yet AGAIN!
Geeze...please let me keep my motherboard for 6 months!
Some of them are busy fapping to the pic right now, so hush. You'll spoil the mood.
It's about effing time... maybe chip manufacturers have finally clued in that cache is the single biggest characteristic of a processor that affects (NOT impacts) performance. I have seen far too many 2-3GHz chips crippled by insufficient cache over the years, but hey, it was $20 bucks cheaper and the same speed so it must be a better deal right? Too bad that this will probably not make the market and the cache will be cut back to 64KB per core to shave a few dollars off the price and suck more people in to buying crippled gear...
Why don't they just release the CPU? I mean they have it working, they tested it and stuff.
I'm not trolling, I'm just curious to find out what changes a processor goes through in it's last months before being launched.