AMD Announces August Release Date for Barcelona
An anonymous reader writes "Rumors said the release wouldn't be until late Q4 but an August ship date is now promised for AMD's quad-core chips. They're only releasing up to 2.0 GHz processors at first, with the top speed devices coming out later in the year. 'AMD's Barcelona puts four cores on a single slice of silicon, an approach AMD calls native quad-core, and the company has argued that Barcelona will outperform the Xeon 5300. The only problem: that comparison soon will become obsolete. Intel's second-generation quad-core server processors, Harpertown a server member of Intel's Penryn family, will arrive this year, too, with the promise of better performance, lower power consumption and lower manufacturing costs by virtue of a manufacturing process with 45-nanometer features. AMD is only just now moving to a 65-nanometer process.'"
Lowering the costs of manufacturing may be nice, but I don't think it's a particularly significant factor in their pricing model.
Thanks, anyways.
AMD is only just now moving to a 65-nanometer process
That's a nice thought, except it's totally wrong. All their Brisbane core X2 chips are on 65nm now, and have been for quite awhile.
Moving to native quad core has a lot of advantages and I'm actually excited to see how well this CPU will perform. Critics that claim that AMD lags behind in the process size would do well to note that AMD has ALWAYS lagged behind Intel in that category, and, yet, has managed to not only survive, but prosper.
This is my sig.
Wow, it'll be 6 or 7 usable ghz of computing power! WOW! We're a whole 1.4% of the way to that 500ghz CPU power that we were talking about in yesterdays article! Can you smell it? The future is coming!
*snicker*
I hope they manage to avoid the problems that hit Intel's Core 2 Duo, and squash some of their own bugs while they're at it. Or is it too late to handle those problems at this stage in the manufacturing process?
"What do you think?" "I think 'What, do you think?!'"
Intel maxes out at 4 cpus and there plan to have 4 FSB in there upcoming 4 wat xeon chip set and CSI has been pushed back to 2008
Games can be specialized to use 4 or more cores.
Servers will really use it.
Mr. PC enthousiast who likes to rip DVDs and do other things in the meanwhile can do with 2 cores.
I'm a multitasker who converts audio and video and downloads a lot while intensively browsing the internet. I see no need for me to go more than dualcore. If you are like me; better yet use the money on more happy HD-space, quiet cooling and memory.
If you mod this up, your slashdot background will turn into a beautiful sunset!
It is unfortunate, because the only reason Intel killed off the poorly designed Pentium 4 was the strong competition, and the only reason you can buy a Core 2 Duo for under $150 is the competition from AMD. AMD is showing that it costs them more to make worse chips than Intel - since they have no choice, they are selling them at price points that often make them a great value, especially if you don't need the best performance per watt. But AMD isn't making enough profit to do the development they need to catch up. Note to IBM: buy out AMD and set them on the right path before it is too late. There is great potential in their CPU designs, but without more cash and technology to speed up development to compete, they will die a slow death.
I can understand that there would be a difference between chips designed for multiprocessing, but if I wanted to have a single-chip workstation, would there be any difference between the Barcelona and the Phenom?
I'm interested in building new workstations for my company, and the Phenom chips look great except that they don't exist, and won't, for at least six months. Why not build Barcelona workstations, though?
Thad Beier
I love Mondays. On a Monday, anything is possible.
I don't think the battle is only on the 45 vs. 65nm arena. There are other interesting technologies in the package that deserve some consideration. Barcelona will include Nested Page Tables (NPT) technology, which could potentially give a significant performance boost to memory intensive applications running on virtual machines once the hypervisors start supporting it.
Intel will also be coming out with a similar technology called Extended Page Tables or EPT, but AFAIK their timeframe is early 2008.
AMD is using SOI, which as I understand, produces some benefit over Intels process at a given process size. If the benefit offsets 65 v 45, or comes close, I don't know.
I do know that AMD sales have persisted in high-performance applications, simply because AMD's memory and IO architecture remain *much* metter than Intel's. Intel with Core 2 finally seriously had a competitor in terms of performance (i.e. very good floating point), but it will be interesting if Barcelona essentially matches the performance in terms of floating point and such, but maintains (or widens) the memory performance, it could be an interesting time for AMD once more.
XML is like violence. If it doesn't solve the problem, use more.
moderators seem to be very harsh today
this should be moderated funny imho (the tomatoes part made it funny)
on another note i hope this chip is killer because it deserves to be !
i saw this chart which iirc eventually meant every core on the amd can be controlled
frequency wise and vcore wise although i'm not sure about the latter
The problem is that Intel will not implement anything AMD comes up with unless AMD can convince enough software companies to switch their products to the AMD developed standards. For example way back, they created 3dnow! instructions and had minimal success even though there were some obvious performance benefits. Intel never implemented 3dnow and instead went with SSE. It's pretty obvious who won that battle. Now AMD did have a win with AMD64/x86-64, but progress there has been slow and Intel still doesn't want to admit defeat by relabeling the supported instructions as EMT64. If AMD wants to truly win the instructions standards battle, they would have to focus more effort on gaining market share and software partnerships first.
Another thing to note is that while they do typically lag behind one version of SSE, they did implement a number of improvements to SSE instruction performance in barcelona. Hopefully these improvements will shorten the gap on SSE heavy benchmarks (optimized encoding software, games).
Look out Slashdotland, it's the incredible edible run-on sentence!
The early Barcelonas will be designed for dual socket servers, and they'll be released at reasonably low clock speeds. If you want to make an 8 core workstation that isn't super fast on single threaded tasks, then they'll be a great deal. If you want a single socket system, you'll be spending more money for lower speeds than if you waited for the Phenom processors.
-- The act of censorship is always worse than whatever is being censored. Always.
When have you ever seen a game benchmark changed by the difference between SSE2 support and SSE3 support? From what I've seen, most game developers don't even consider using the new SSE instructions for a couple years - both waiting for AMD to support them and waiting for people to replace the vast majority of older Intel machines that don't support them.
Even when chips do support SSE type instructions, they rarely produce as drastic a performance improvement as the chip manufacturers hype would imply. Writing a program for SIMD parallelism (like SSE) is just as hard as writing it for a multi-core processor, and works for far fewer workloads.
-- The act of censorship is always worse than whatever is being censored. Always.
The only OS support for SSE(x) is saving/restoring the registers while doing a context switch.
Do you even lift?
These aren't the 'roids you're looking for.
AMD and Intel have cross-licensing deals that handle the instructions that each company creates... these deals go way back to the mists of x86 time. So, for AMD to implement SSEn there is no legal problem. Ditto for the reverse. Except, the "problem" is that Intel w/80% of the market can pretty much dictate what instructions will survive in the market -- with the big exception of x86-64, and potentially some of the new virtualization stuff.
Now, about releasing chips in a timely manner... the trick is Intel doesn't have to tell anyone about the new instructions until they are well on their way to being in Intel CPUs. AMD finds out about these things at the same time as software developers get the promotional material from Intel. There's no way for AMD to release chips with these functions at the same time as Intel - they have to wait until the next moderate chip revision.
Does it matter? Usually not. Most software lags instruction changes by years. The exceptions are typically where performance really counts. For example, video encoders picked up on SSE2 pretty quick, since it provided dramatic improvements for their code.
Intel doesn't max out at 4 CPU's, at least not for systems you can actually buy. Since the memory bandwidth isn't there the most you can buy is dual quad core (this is from IBM, HP and Dell). Oh and they max out at 32GB of ram whereas you can get a DL585g2 which can economically go to 64GB and maxes at 128GB with 4GB chips. HP and AMD have committed to supporting Barcelona on the DL585g2 so I expect I will have some 16core 64Gb machines by the end of the year =) Oh and if you are into Sun the x4600 will be able to go to 16cores and 256GB of ram once Barcelona ships.
There are 4 boxes to use in the defense of liberty: soap, ballot, jury, ammo. Use in that order. Starting now.
I've written video processing code using SSE, and it makes a substantial speed difference. I haven't looked at the numbers recently, but my recollection is about a 30% reduction in run time. Beyond having to learn more assembly language instructions, writing for SIMD is not terribly difficult. Writing for a multicore processor requires learning about threads and paying attention to data timing, which I find quite difficult.
Contribute to civilization: ari.aynrand.org/donate
Oh and they max out at 32GB of ram whereas you can get a DL585g2 which can economically go to 64GB
Gosh, I sure wish HP would put an Intel processor in the DL580g4. That way there'd be a platform that would max out at 64GB of ram. Oh, wait...
Education is a better safeguard of liberty than a standing army.
Edward Everett (1794 - 1865)
Yea, video processing code is the poster child for SIMD - a 30% runtime improvement there over no SIMD is quite reasonable. On the other hand, the difference between SSE2 and SSE3 for the same code is probably somewhat smaller. In other areas, SIMD doesn't help at all, or only helps if you use techniques that are much more complex than multi-threading code.
Another interesting development is GPUs as general purpose SIMD processors...
-- The act of censorship is always worse than whatever is being censored. Always.
There is a diffrence. AMD has to pay to license Intel patents...
http://news.com.com/2100-1040-257059.html
http://news.zdnet.co.uk/hardware/0,1000000091,391
So everything AMD invents can be adopted by Intel for free. But AMD has to pay license fees to Intel. Pretty indefensible really, since Intel has a much larger market share, and much higher proft margins.
echo -e 'global _start\n _start:\n mov eax, 2\n int 80h\n jmp _start' > a.asm; nasm a.asm -f elf; ld a.o -o a;
Wow, and the DL580 doesn't support the 5300, so no quad core with large memory support. So unless you are doing one of the small subset of HPC problems that needs pure CPU performance there's very little need. The fact is the Intel systems run out of ram before they run out of CPU power for most real world datacenter needs.
There are 4 boxes to use in the defense of liberty: soap, ballot, jury, ammo. Use in that order. Starting now.
Currently, Intel's Core-based Clovertown is only available for 2-way motherboards (with two independent FSBs). Intel's 4-way boards still use the Netburst architecture and two FSBs for four CPUs. Tigerton and Clarksboro (the Caneland platform) will update Xeon MP to the Core architecture and four point-to-point buses.
TO START
PRESS ANY KEY
Where's the 'ANY' key? I see Esk, Kitarl, and Pig-Up...
I think that's a misprint. It should be "AMD doesn't get to collect royalties from Intel for any patents Intel might adopt."
echo -e 'global _start\n _start:\n mov eax, 2\n int 80h\n jmp _start' > a.asm; nasm a.asm -f elf; ld a.o -o a;
No one has voiced it yet, but AMD's 65nm process is a failure. It's 65nm parts overclock worse than processors at 90nm process and that's probably why AMD are still producing all there high end parts at 90nm
8 hyperthreading cores running 8 threads each, with each core having 2 ALUs and 1 FPU.
Processing power over cost makes this expensive. Besides, notice how they say "hyperthreading" and threads... this isn't the same as "real" cores. Try loading up those threads and you will watch single thread performance drop like a rock on the T2000. We have this Java app, opens up 1GB RAM and 96 threads of execution. A E240 was more than 1.5 times as fast with 4 cores than the loaded T2000.
I am looking forward to AMDs 4 core...hyper threading is a joke.
First of all, there are true 8 cores on a T1 (Niagara) chip (T2000 is the server if memory serves me right). There are 4 threads per core, which make sure that the ALU's and FPU's are used to the full. Now, there was some problems with floating point operations and crypto operations because not every core possessed these functionalities. The Rock processor, with 16 "processing units" (4 cores, 4 processing units each), 16 FPU's and crypto-processors will set this right.
Note that these chips are created to deliver a good application server performance, while still showing a strong price point and power/performance ratio. If the data I found it correct, each T1 processor uses something like 56 Watt to do what it has to do. I wonder if your little test took this seriously, using two AMD CPU's running full speed. Also, if anywhere possible, loading the chips with 96 threads will make the scheduler go ape. Better use a thread pool of 8 threads (or 16 or 32) instead. So even if AMD comes out with this 4 core
But I agree on one thing: hyperthreading does very little. I would be just as happy with a T1 using only two threads. Two threads on a single core sometimes can make a 10-20% performance difference. If Intels hyperthreading is any indicator, this difference can go either way. I created a crypto cracking application which run much *slower* when hyperthreading was enabled (using 8 threads out of convenience). If hyperthreading is not (or cannot be) done correctly, it's better to leave it out altogether. It seems that the notion of processing units on the Rock processor targets this issue.
8 hyperthreading cores running 8 threads each, with each core having 2 ALUs and 1 FPU.
That's 64 concurrent threads, 16 ALUs, and 8 FPUs. And probably only needs a 150- or 200-watt power supply. There's a reason why Sun is getting something like $20K per UltraSPARC T1000 or T2000 rack-mount systems and can't keep up with demand...
Um, if you're talking about T1000 and T2000, that's 32 concurrent threads, 8 ALUs and 1 FPU. And the T1000 and T2000 start at $3995 and $9995, respectively. And lead time isn't any worse than their traditional single-core UltraSparc III based systems.
It's an apples to oranges comparison, anyways. Niagara has a wholly different design philosophy and a different set of trade-offs. The T2 cores are far more capable than the T1, but they are still relatively primiative compared to anything Intel or AMD are putting out, latency on common instructions and memory access are (often drastically) slower, and the clock speeds are significantly lower. The high concurrency successfully counter-blances the relatively low speed and high latency in certain workloads, but got spanked in real world tests (including web servers and databases, their target market) in benchmarks.
Apples to oranges. Niagara's design is based on lower speed, relatively primative cores using register switching to allow a lot of "concurrent" threads (most of which aren't actively executing at the time). They went with masking latency instead of reducing it (which, ironically, is pretty well the opposite of the UltraSparc III).
This is exactly right. One of my best friends is an engineering manager at Intel, and he's been there for 9 years now, and he survived the 1000 manager cut recently. A couple of years ago, when AMD was kicking Intel's butt, he said "just wait about 3 years". I thought he was just blowing smoke, but he was right. He recently told me that when AMD burst onto the scene with the Athlon and started trouncing Intel, Intel took it very seriously. There were many meetings about what to do, and they had people do reasearch.
He said they were in a large meeting with some higher-ups, and he saw a presentation that outlined the move to 45nm. He said after that meeting, nobody there was worried at all about AMD because they knew it was a matter of time. They knew AMD didn't have the financial or research resources that Intel had, and THAT is what it takes to get ahead. So they bided their time, did what they needed to do, and trounced them.
He said there was also talk about how brash AMD was, and how the execs would drive their flashy cars around, and be just blowing money right and left. The Intel execs were more subdued because it wasn't new money to them. Tortoise and the hare. There was some back and forth, but it will be a LOT harder for AMD to compete now than it was for them to come up. They woke Intel up, and they aren't stupid. My friend acknowledges, and said everyone at Intel does as well, that AMD coming onto the scene was a great thing for Intel. It made them get off their lazy asses. Not to mention what it has done for the computing industry.
My beliefs do not require that you agree with them.
Well, SSE matters much in HPC code. Intel compiler has quite decent vectorizer which helps a lot. And writing vectorizeable code is not that hard, actually.