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AMD Multi-Core G3MX DRAM Interface Details Emerge

Posted by ScuttleMonkey on from the new-toys-all-the-time dept.

MojoKid writes "New details have emerged regarding AMD's upcoming G3MX technology. The 'future Opteron Platform' AMD mentioned in their press release seems to be built around a CPU currently codenamed 'Hydra'. Hydra will still feature an on-die memory controller, but unlike current platforms it will be geared for DDR3 memory. The processor will interface to one or more G3MX chips, which in turn provides the interface to the memory slots. G3MX will act as a memory port extender for the memory controller in the CPU socket and a serial link to the RAM.The electrical signaling between the memory controller and G3MX is based on HyperTransport 3.0."

2 of 43 comments (clear)

  1. Re:DDR3? by CajunArson · · Score: 4, Informative

    Don't confuse graphics DDR3 with DDR3 SDRAM used for general system memory. They are completely different beasts.

    --
    AntiFA: An abbreviation for Anti First Amendment.
  2. Actually... by Brane2 · · Score: 5, Informative

    this concept seems quite sensible.

    They are using G3MX chips as a sort of multiplexer and connecting it to the CPU though a couple of lanes with high-speed signaling.

    Internal logic within HYDRA CPU will have the capability to use either conventional onboard memory controller and drive the DDR-3 RAM directly or when socketed within board with G3MX extenders, use that same lines for communication through the G3MX.

    Since the load on the lines will be much smaller and constant and since all lines are unidirectional, each line will be capable of much higher signaling speed, so they will be able to use 4x as much RAM as before per CPU node.

    If that is not enough, several Hydra CPUs could be connected through HT links- just like now with existing Opterons.

    CPU-G3MX connection is much more direct and probably need not to use extra cycles for node addressing, unlike conventional internode communications through HT links, so time overhead could be considerably smaller...

    Also, compared to FB-DIMMs, when accessing to some RAM bank here user only pays some throughput penalty (if any), but doesn't suffer much extra latency- with FB-DIMMs data hos between the modules and each hop costs one clock, so access time for 4-th module is longer than to the first one in a group.

    Not to mention that GMX-3 chip could host some L3 cache if needed in some later implementation and that combined speed of all G3MX chips is probably greater than existing solution, so interesting effects could be achieved with meory interlieve.

    It could very well be that such combination could have distinct speed advantage even in many workstation applications...