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AMD Multi-Core G3MX DRAM Interface Details Emerge

Posted by ScuttleMonkey on from the new-toys-all-the-time dept.

MojoKid writes "New details have emerged regarding AMD's upcoming G3MX technology. The 'future Opteron Platform' AMD mentioned in their press release seems to be built around a CPU currently codenamed 'Hydra'. Hydra will still feature an on-die memory controller, but unlike current platforms it will be geared for DDR3 memory. The processor will interface to one or more G3MX chips, which in turn provides the interface to the memory slots. G3MX will act as a memory port extender for the memory controller in the CPU socket and a serial link to the RAM.The electrical signaling between the memory controller and G3MX is based on HyperTransport 3.0."

4 of 43 comments (clear)

  1. good luck AMD by edxwelch · · Score: 2, Interesting

    It'll be interesting to see if AMD actually get to deliver this technology before they run out of money (http://uk.theinquirer.net/?article=41700)

  2. Re:PowerPoint City! by eniac42 · · Score: 4, Interesting

    Despite the propoganda they are not pure angels and Intel is not pure evil either.

    Maybe so, but thats not the point. I just dont want to see the mainstream PC processor market to become a one-horse race. If AMD had not been there, Intel would probably still be making P4s clocked at 1ghz today.. Having said that, I dont think AMD can take Intel head on - they are right to (or need to) find other niches..

    --
    "A nation that forgets its past is doomed to repeat it." - Churchill
  3. Re:Actually... by raxx7 · · Score: 3, Interesting

    Intel, IBM et all have been using similar memory extenders on server chipsets for quite some time.
    For example, check the XMBs on Intel's E8500 chipset.

    The reason why Intel has moved from such memory extenders and pushing FB-DIMM is simple though: there won't be a 4th DIMM on G3MX. DDR3 isn't likely to support more than 2 registered DIMMS per channel, 4 rank each.

  4. "Based On" Hypertransport 3.0? by Courageous · · Score: 2, Interesting

    Something bugs me about the chart in TFA.

    It shows 13 lanes outgoing and 20 lanes incoming to each G3MX unit.

    And then it references hypertransport. However, hypertransport is a duplex standard. It can transfer data 20GB/sec in each direction per 32bit link.

    So how am I to interpret this.

    Anyway, supposing that each of those 3GMX units is anything at all similar to an 32-lane HT3.0 protocol, we're talking 80GB/sec of memory bandwidth per processor. That's just nuckin' futz! :-)

    C//