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Breakthrough May Revolutionize Microchip Patterning
Stony Stevenson writes "US research engineers claim to have developed a low-cost technique that allows them to create ultra-small grooves on microchips as easily as 'making a sandwich'. The simple, low-cost technique results in the self-formation of periodic lines, or gratings, separated by as little as 60nm, or less than one ten-thousandth of a millimetre. From the article: 'The new 'fracture-induced structuring' process starts when a thin polymer film is painted onto a rigid plate, such as a silicon wafer. A second plate is then placed on top, creating a polymer 'sandwich' that is heated to ensure adhesion. Finally, the two plates are prised apart. As the film fractures, it automatically breaks into two complementary sets of nanoscale gratings, one on each plate. The distance between the lines, called the period, is four times the film thickness.'"
Generally I throw my sandwiches away when they get a film on them.
The chips are groovy. Very groovy.
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Must be a sufficiently advanced technology then...
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The selling point of this "new" technology is "low cost". The lithography at sub 100nm is getting extreme pricey.
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Here's my notes on silicon semiconductor manufacturing, but this 'polymer sandwhich' method is entirely new to me. From what I can recall, manufacturing tactics usually include chemical etching with masks to make marks into the wafer or sometimes with specialized lasers. From the summary of the article, it looks like this latest process lets us do periodic lines via adding mechanical energy so that we fracture the plates. Ironic, since we usually try to avoid fracturing our wafers. ;)
So this method is interesting, but the resolution of these gratings is only 60nm. Other experimental groups have achieved a resolution as small as 30nm (http://willson.cm.utexas.edu/research/index.php). ..and Intel is already producing chips at 45 (http://hardware.slashdot.org/article.pl?sid=07/08 /20/1611202/)
chillax137
Additionally, there are so many announcements like this that you have to see it on the market to believe it.
What are you going to wait out, exactly? Are you an executive at a chip-producing firm with the power to decide to use this?
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I agree the cost is high (for the FABs) but more to the point, while this is an interesting new manufacturing method, its not likely to be such a big advance, (for the chip industry) as the title to this news implies. Also I think that around about 2011, they are talking about having production 32nm fabrication. So within about 4 years from now, 32nm is going to seem very small, compared with this relatively large 60nm groves in the chip.
Where this technology sounds potentially very useful, is in maybe applications like sensors. As its nano-scale patterns can be applied to large surface areas. That could potentially be very interesting.
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The actual scientific paper can be found here (subscription required). This is a very neat idea, similar to buckling-induced experiments where similar nano-patterns can be produced quickly and easily in polymeric materials. The micrographs in the paper show remarkably clean and consistent structures, with well-defined periodicity and cross-section. From a scientific point alone, it's quite remarkable to see how one can harness a usually random process (fracture) to generate well-defined nanostructures.
That having been said, this technique suffers from a few limitations. Firstly, it will be difficult to scale this down to arbitrarily small features: polymer film stability becomes increasingly difficult as the film thickness is decreased, so this technique is unlikely to scale cleanly below the 60 nm they've already demonstrated. Also, this technique generates a large-area pattern, but it doesn't appear possible to control the registry of this pattern. So, this could perhaps be used as the first step in a mult-step chip patterning, but if you can't align subsequent patterns, it becomes useless for generating complex multi-layered structures for chips. (I can imagine ways to overcome this, but it wouldn't be easy.)
As such, I really don't think this is going to "revolutionize microchip patterning" as the headline implies. I don't think this will ever be used to generate smaller and smaller chips: the current challenges in the industry for next-generation processes are beyond what this technique can do. (Besides which, it doesn't integrate particularly well into the current photo-lithography infrastructures).
However, as a lower-cost alternative for fabricating nanostructures in the micron to 100 nm size regime, I could see this being useful. It's an easy way to create a large-area array of remarkably consistent patterns. It could be used to create optical gratings, or as a template for assembly of proteins (for diagnostics, etc.), or templates for magnetic domains (in hard-drives, etc.) and many other fields.
Well 'pricey' is a relative term... if you're talking about the setup-cost for a factory that produces IC wafers, then yes you're talking enormous investments before the first wafers run of the production line with decent yields. But from an end-user point of view, you can buy a $50 CPU or memory module these days that may contain several hundred million transistors. Something equivalent being non-existent or 10 times more expensive a few years back...
I'm wondering more about practical applications, and how long they will take to hit the market. For regular structures, all sorts of semiconductor memory comes to mind. Cheap flash memory? Affordable solid state drives with capacities equal or bigger than magnetic disks? For such applications production errors may not matter much. If the process is cheap, add enough redundant memory cells, decent bad cell/sector management, and the end result could be very useful.
Anyway, looks very promising. We'll see what comes of it...
how is it a breakthrough you say...
Lets see...
They've come up with a similar (faster/cheaper) means of making something. The entire point of the article is that this new method is far easier and faster then old methods. Not to mention the fact alone that it's utilizing mechanical force to etch a chip which is unheard of... besides this could be very practical. Think about it, most companies don't need an overpriced chip with 45nm spaced etchings... but being able to buy many cheaper chips with a 60nm gap would be a great.
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Indeed. The line-edge-roughness is becoming a bigger and bigger issue as the lithography industry searches for what to use for next-generation patterning technology. Based on the talks I've been to (I do research in a related field), the large efforts that were put into developing "extreme-ultraviolet lithography" (EUV), which would use 13.5 nm illumination, are not working out. The technology is not ready (e.g. they still don't have a light-source operating at that wavelength that generates enough light...) and is very much more expensive than anything we're using today. Many in the research end are now thinking that we cannot depend upon EUV to fill the future roadmap nodes.
I agree that there are going to have to be some big changes. Some sort of disruptive technology is going to be needed. One promising area is the rather simple concept of "nanoimprint lithography": where instead of using light to shine through a mask and pattern a polymer resist (which is then used to etch patterns into the silicon), you physically press a single (reusable) high-fidelity (high-cost) mask into a polymer, at a temperature where the polymer is liquid-like. The patterned polymer resist can then be used to etch Silicon in the usual way.
This physical embossing has been shown to generate pattern fidelity way beyond what you would naively expect: sub 30-nm feature accuracy has been demonstrated. Nanoimprint is a comparatively simple and cheap methodology. When combined with the other recent advances in lithography infrastructure (like high-precision registry alignment systems), it seems quite plausible that nanoimprint will be able to deliver the features required for next-generation chips. Of course, many details need to be worked out, but it's a very promising, and rather disruptive, new technology (and has been added to the ITRS roadmap).
I don't think it is as important for FAB plants as much as it is bringing influence from the small consumer into hardware. If the cost comes down enough we can take old designs or open designs and actually be able to produce relatively small quantities of modified hardware for cheap.
This would go hand in hand with the concept of OSS cause as OSS enthusiast's are intrigued by this kind of thing products like that completely OSS graphics board which never really took off would be much more attainable. With an interface like PCI-Express if the community would be able to design an 'open-board' concept, with multiple open sockets on the board its self, you would be able use the daughter board as an OSS motherboard and control it by use of an open interface.
Picture a PCI-E board with one controller on board and a handful of open PGA sockets. A company or group develops a physics, encryption, sound, graphics, firewall chip that gets installed on the board and you could access each one for its resources via the PCI bus. Each chip would likely be more expensive then the closed proprietary brothers but the market is there. Lets say your business has a project that is naturally lopsided in terms of processing, you could fabricate a processor to even it out, or make a self sufficient board utilizing the PCI bridge for nothing more then access to memory and VCC.
This would really be an eye opener as OSS could effect more then just the software market but the hardware market as well. You could have a board with optical, RJ45, DVI, DVB-S2 all on the same board and each socket could potentially have access to each port directly or via on board controller (similar to a north bridge) condensing a sound controller or a network controllers logic onto a 60nm process would be night and day compared to what we have, this could potentially lead the way to the entire machine being designed using this "sandwich" process.
Personally I think development along the lines of the killerNic type of hardware would revolutionize computing. Imagine owning a machine with multiple optical outs that you could use for networking or to hookup to a TOS-link device, the card would have its own processor running customized microcode. Maybe as a temporary storage device similar to flash drives but internal running of a 16x slot would bring efficiency of any system up 100 fold. Eventually all these separate ideas would distill into an open command set that could be implemented into a CPU type of application. A CPU with instructions built-in from the best of encryption, graphics, sound, filtering hell even regex. We could even vote on which registers should be included in the final design.
So you know one person out here thinks this is cool, maybe more will come of this.
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