Researchers Design Microchip Ten Times More Efficient

WirePosted writes to mention that a new highly efficient microchip has been announced by researchers from MIT and Texas Instruments. The new chip touts up to 10 times more energy efficiency than current generation chips. "One key to the new chip design, Chandrakasan says, was to build a high-efficiency DC-to-DC converter--which reduces the voltage to the lower level--right on the same chip, reducing the number of separate components. The redesigned memory and logic, along with the DC-to-DC converter, are all integrated to realize a complete system-on-a-chip solution."

Comments

Will we get these soon?

[Naughty Bob]

The article doesn't say whether these chips are cheaper to make than the current technology. That will be the deciding factor regarding how soon these make their way into our portable devices.

Re:Will we get these soon?

[Shikaku]

The processors, chances are, are not very useful for things that require more processor horsepower. The article mentions use in things that could be powered by minuscule power input (i.e, body heat). I think it was invented for that purpose, that the power bill will be minuscule at worst, nonexistent at best for these things. Therefore, use in portable devices for now are not so much, except maybe a simple PDA that requires no batteries, only heat.

Re:Will we get these soon?

[misleb]

Combining computer and girlfriend: FAIL

Dup?

[Bob-taro]

I thought this sounded familiar.

Any chance of commercial success?

[damn_registrars]

The first thing that came to mind when I saw this article was the Transmeta Crusoe processor. Which unfortunately never achieved much of any significant market penetration. Indeed, it seems that you really have to have something more than just an incredibly efficient chip in order to compete against the Intel - AMD behemoth.

Personally, I would love to see a chip that requires very low power make it into the mainstream market. I think it would great to have something like that for the miniITX form factor or something of that nature that hobbyists could tinker with and find fun applications for. The Transmeta, unfortunately, never realized that as far as I ever saw.

Re:Any chance of commercial success?

[ejtttje]

I don't think they're demonstrating a particular CPU, but a technology or design strategy that can be built into *any* chip. So Intel or AMD could pick up this research with their own chips. (subject to patents and licensing of course)

Also, from the article: "So far the new chip is at the proof of concept stage. Commercial applications could become available "in five years, maybe even sooner, in a number of exciting areas," Chandrakasan says

Re:Any chance of commercial success?

[PPH]

That depends on youe definition of 'the mainstream market'. This technology may never appear in desktop/laptop PCs, but become popular in handheld devices where power consumption is a major issue. There is a limited amount of power saving economically feasible in PCs as long as the displays and other peripherals continue to be major power hogs.

Another interesting market might be in server farms. But I wouldn't count on this driving the market. CPU architectures specific to servers haven't sold well, so this isn't an economically viable niche.

Microcontrollers are a large enough market segment to justify the R&D. I forget where I read this, but if you take the total percentage of the uP and uCs installed in PCs and round it to the nearest whole percent, that number is zero.

Re:Any chance of commercial success?

[Phat_Tony]

Transmetta had radically better power consumption for a while and might have some day come to dominate the portables market, had they retained an advantage like the one they had at their debut. Transemetta's problem was underestimating how rapidly Intel could improve the power efficiency of their chips. In response to Transmetta, Intel suddenly got serious about power consumption and got competitive so fast it left Transmetta with little to differentiate their chips from the competition.

Like anything, the commercial viability of this doesn't just depend on how much better it is than what's already out there, but on how long it'll take their competitors to catch up.

Transmetta didn't do so well, but the real winner of Transmetta's actions was the consumer. Transmetta drove Intel and AMD to improve efficiency much more rapidly than they had been. Let's hope this new technology makes it into production and does the same.

Cutting to the chase

[objekt]

Just like all these articles on breakthroughs in energy efficient technology, there's only one thing I'm interested in.

from TFA:

So far the new chip is at the proof of concept stage. Commercial applications could become available "in five years, maybe even sooner, in a number of exciting areas," Chandrakasan says.

Re:Cutting to the chase

[Jerry Coffin]

This seems to be a complete other kind of advancement than regular chip evolution we've seen so far.

There's not enough in TFA to say for sure, but I'd guess rather the opposite. The main thing they mention is a lower power supply voltage. Power supply voltages have been dropping steadily for a long time. Once upon a time, the most common logic family was the 7400 series, which all used 5 volt power supplies. Somewhat later 3.3 volt CMOS logic was introduced. Most CPUs, memory, etc., now use somewhere between 1 and 2 volts.

For the most part, you get a trade-off between voltage and speed -- with a higher voltage, you can charge up a more reactive load more quickly, giving faster rise and fall times. That translates directly to higher bus speed.

At the same time, the power you use is the product of the voltage and the current, so as you raise the voltage you raise the power usage. Worse, the current you drive through a given impedance also rises linearly with the voltage -- so the power usage is proportional to the square of the voltage.

That (probably) explains to a large degree how/why they've reduced the power usage by a ration of 10:1 by reducing the voltage by a ratio of something like 4:1 (in theory, a 10:1 power reduction should imply a voltage reduction by the square root of 10, roughly 3.16).

In any case, however, nothing in the article really suggests that they've departed a great deal from the path everybody's been following for quite a while. Of course, they may have done something truly radical here -- but based on what they've said, that isn't necessarily the case.

This is simply an experiment in voltage scaling!

[Terje Mathisen]

As the MIT report states, the key was to make the chip operate at 0.3 V instead of ca 1.0V

Since power usage is (roughly!) proportional to voltage squared, getting the chip to run at less than one third the usual voltage will indeed give an order of magnitude reduction in power usage.

From the report:

One of the biggest problems the team had to overcome was the variability that occurs in typical chip manufacturing. At lower voltage levels, variations and imperfections in the silicon chip become more problematic. "Designing the chip to minimize its vulnerability to such variations is a big part of our strategy," Chandrakasan says. I.e. current state of the art transistors does not work reliably at such voltage levels, I'm guessing that they have to give up significant parts of the theoretical power reduction in order to make it work at all.

Terje

Re:I wonder where it will be built at?

[Bob-taro]

It seems like all of American know-how goes into designing things like this, then companies move the jobs overseas ...

The researchers are: "graduate students Yogesh Ramadass, Naveen Verma, and Joyce Kwong, along with Professor Anantha Chandrakasan". While they may very well all be U.S. citizens, it makes me want to ask for a precise definition of "American know-how".

Interesting but what about variability?

[quo_vadis]

Their work is definitely interesting, but I think some important questions remain unanswered, the main among them is the tradeoff between correctness of operation vs. performance because of variability. There is a paper in ISLPD 2006 which shows that for a 65nm circuit to operate at 0.3 V, the clock period must be scaled up by a factor of at least 230% to compensate for variability related issues. Additionally, there is a huge problem as far as tool support goes. This is not just mix-and-match style design. In order for this to have widespread use, it needs to work well in the EDA tool workflow. This means that libraries (and to some extent transistors) need to be characterized well at the subthreshold operating voltages. This causes a catch-22 situation. In order to design something using this subthreshold voltage technology, you need good transistor models, but the fabs have no interest in providing these models unless there is large customer demand. It is pretty expensive to get good models. The way this works is most fabs actually create transistors/gates at the given feature size, characterize them, including parameters for variation/process variability and give these to their customers, who design their chips based on these simulations. The reason these are so important is that for synchronous circuits, you have to base the design of the clock scheme on the worst/average case delay, and this you can get only by doing complete (usually Monte Carlo based) simulation of the chip using the transistor models that fab gives you. If you base the parameters solely on simulation based tools, you ignore all sorts of effects in the real world, causing a massive drop in yield(i.e. working chips made by fab).

Re:I wonder where it will be built at?

[Bob-taro]

I take it you haven't been inside an engineering college lately.

Even when I was in engineering school, the majority of graduate students were foreign. I forget where, but I once read a quote that went something like this: "American universities are the best in the world. In fact, they are so good that American high school graduates can't compete in them".

Re:I wonder where it will be built at?

[gnick]

The researchers are: "graduate students Yogesh Ramadass, Naveen Verma, and Joyce Kwong, along with Professor Anantha Chandrakasan". While they may very well all be U.S. citizens, it makes me want to ask for a precise definition of "American know-how". You were expecting to see "graduate students Geronimo, Running Bear, and Pocahontas, along with Professor Hithawea"?