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Researchers Design Microchip Ten Times More Efficient
WirePosted writes to mention that a new highly efficient microchip has been announced by researchers from MIT and Texas Instruments. The new chip touts up to 10 times more energy efficiency than current generation chips. "One key to the new chip design, Chandrakasan says, was to build a high-efficiency DC-to-DC converter--which reduces the voltage to the lower level--right on the same chip, reducing the number of separate components. The redesigned memory and logic, along with the DC-to-DC converter, are all integrated to realize a complete system-on-a-chip solution."
The article doesn't say whether these chips are cheaper to make than the current technology. That will be the deciding factor regarding how soon these make their way into our portable devices.
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I don't think they're demonstrating a particular CPU, but a technology or design strategy that can be built into *any* chip. So Intel or AMD could pick up this research with their own chips. (subject to patents and licensing of course)
Also, from the article: "So far the new chip is at the proof of concept stage. Commercial applications could become available "in five years, maybe even sooner, in a number of exciting areas," Chandrakasan says
Transmetta had radically better power consumption for a while and might have some day come to dominate the portables market, had they retained an advantage like the one they had at their debut. Transemetta's problem was underestimating how rapidly Intel could improve the power efficiency of their chips. In response to Transmetta, Intel suddenly got serious about power consumption and got competitive so fast it left Transmetta with little to differentiate their chips from the competition.
Like anything, the commercial viability of this doesn't just depend on how much better it is than what's already out there, but on how long it'll take their competitors to catch up.
Transmetta didn't do so well, but the real winner of Transmetta's actions was the consumer. Transmetta drove Intel and AMD to improve efficiency much more rapidly than they had been. Let's hope this new technology makes it into production and does the same.
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Their work is definitely interesting, but I think some important questions remain unanswered, the main among them is the tradeoff between correctness of operation vs. performance because of variability. There is a paper in ISLPD 2006 which shows that for a 65nm circuit to operate at 0.3 V, the clock period must be scaled up by a factor of at least 230% to compensate for variability related issues. Additionally, there is a huge problem as far as tool support goes. This is not just mix-and-match style design. In order for this to have widespread use, it needs to work well in the EDA tool workflow. This means that libraries (and to some extent transistors) need to be characterized well at the subthreshold operating voltages. This causes a catch-22 situation. In order to design something using this subthreshold voltage technology, you need good transistor models, but the fabs have no interest in providing these models unless there is large customer demand. It is pretty expensive to get good models. The way this works is most fabs actually create transistors/gates at the given feature size, characterize them, including parameters for variation/process variability and give these to their customers, who design their chips based on these simulations. The reason these are so important is that for synchronous circuits, you have to base the design of the clock scheme on the worst/average case delay, and this you can get only by doing complete (usually Monte Carlo based) simulation of the chip using the transistor models that fab gives you. If you base the parameters solely on simulation based tools, you ignore all sorts of effects in the real world, causing a massive drop in yield(i.e. working chips made by fab).
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