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AMD Fusion Details Leaked
negRo_slim writes "AMD has pushed Fusion as one of the main reasons to justify its acquisition of ATI. Since then, AMD's finances have changed colors and are now deep in the red, the top management has changed, and Fusion still isn't anything AMD wants to discuss in detail. But there are always 'industry sources' and these sources have told us that Fusion is likely to be introduced as a half-node chip."
Great, we finally get cold fusion working (by a chip manufacturer? really?) and the first I hear of it, there's been a leak.
Now we'll never get the NIMBY's to allows us to build fusion reactors.
"Trolls they were, but filled with the evil will of their master: a fell race..." -- J.R.R. Tolkien on Olog-hai
http://www.techweb.com/encyclopedia/defineterm.jhtml?term=half-node
FTFA: "As Fusion is shaping up right, we should expect the chip be become the first half-node CPU (between 45 and 32 nm)"
http://www.maxineudall.com/2010/02/should-economists-be-sued-for-malpractice.html
Was the rush to both a native quad core and quad core on the desktop.
Desktops matter less than less these days. Notebooks are more and more important. You don't put quad core in notebooks yet.
If AMD can pull off Fusion and have it compete with Intel in the laptop space they may actually do well again.
There current problem is they are not competing with the ATOM yet. The netbook may be the next big battle ground. Most people don't want a faster machine anymore. And most laptop users don't want faster laptop. What they want is one that runs longer and is smaller and lighter.
See my blog http://ilovecookes.blogspot.com/ for light hearted technical information.
Without cost and performance (speed) info, this is not really interesting.
Facts in the story:
- AMD using TSMC
- AMD using 40nm instead of 45 or 32
- DirectX 10.1 support with the R800 engine on the chip.
None of this matters unless it does something better and/or cheaper than some other option.
A higher level of integration makes sense for laptops. Putting the GPU with the CPU also makes a lot more sense when we consider that the CPU these days also means the place closest to the memory controllers.
In addition, you have an interconnect between the two which is far faster than anything else available today. However, there is no code today that will use it explicitly, the whole paradigm of a GPU is that you do not read data back to the CPU.
So, for now, the benefits are really physical size and cost. A CPU-integrated graphics core can be better than one placed on the motherboard when you have an integrated memory controller, but a separate card with dedicated RAM should beat both, as long as you do not expect a new "chatty" paradigm of GPU usage.
So, for now, the benefits are really physical size and cost.
Power, more than size. Off-chip buses like Hypertransport are fairly power intensive, and now CPUGPU communication won't have to leave the chip. Depending on how they do the integration with the memory controller, it could also mean that less of the chip needs to be active when doing nothing more than screen refreshes from the frame buffer. But the HT link is a pretty big deal power-wise.
The enemies of Democracy are
AMD has multiple "nodes" per technology. So in 45nm itself, they have 7 to 9 nodes. Each node represents performance improvement over the previous one by using new technology innovations. It is still 45nm technology, but you may add, for example, higher stress liner to improve mobility, hence more current and hence performance. It doesn't change any of the basic groundrules. These nodes are typically in 3-6 months range (rather than 18 month as said by Moore's law). But then these nodes don't really improve performance by 2x either. The first node is the hardest - get the ground rules right, get a yielding process etc. Once the foundation is set, it is relatively easier to experiment with new process technologies.
I can't comment if your description of a "node" is true for AMD or not, but the rest of the silicon industry (via the ITRS roadmap) labels technology nodes like 90nm, 65nm, 45nm, 32nm, 32nm, 16nm, etc, etc...
Historically, the ITRS used the term "technology node" to attempt to provide a single, simple indicator of overall industry progress in IC technology by defining it to be the smallest half-pitch of contacted metal lines on any product (usually DRAM), but they have since abandoned this practice of declaring technology nodes (because various parameters are now scaling at widely different rates). Nowdays, in the rest of the semiconductor industry a node often corresponds to some major process enabling technology (e.g., TSMC 45nm combined 193nm immersion photolithography, strained silicon and extreme low-k inter-metal dielectric material).
If you meant that AMD has 7-9 different nodes that evolved from the 45nm node, I guess that's consistant with this too, but not that consistant with everyone elses' use of "node", they would probably call that a "half-node". If you meant that AMD's 45nm technology uses up to 7 to 9 different scaling factors from other technology nodes I guess that is consistant with this too, but I don't think that's standard industry usage of the word "node".
AFAIK, the industry uses the term "half-node" when the somewhere between the main nodes (e.g., at TSMC, 40nm is considered a half-node from 45nm). Normally a half-node is created by some sort of parametric scaling of some of the features of a regular process node to achieve higher transistor density (generally something theoretically in-reach of a regular process node, by tweaking scaling by different amounts). Of course there are usually several different variety of 1/2 nodes (low leakage, high speed variants, etc) developed. But that's no different than the fact there are many different variants at a particular node in any case.
Often process technology folks design something like a 45nm technology node and after they are comfortable with being able to yield it, they spend some time to tweak it to see if they can get a shrink and if the tweakage good enough, they market it as another "half-node" design point. This is a pretty good tradeoff since they can offer a "shrink" to customer using the main node as a cost reduction exercise or a way to scale customized parts of their designs (e.g., cells, rams, I/O pads) w/o radical redesigns (which might happen between major technology shifts) giving a good !/$ for their engineering efforts.
The reason why many folks think it's weird to design something that probably has a lot of custom stuff like a CPU-GPU hybrid in a half-node is that new things take a long time to design and with processes technology a moving target, it's nice to be able to schedule in a "shrink" and get a low effort cost reduction during the useful sellable lifetime for a product. By starting production in a half-node, to get a cost reduction worth the engineering effort, you'll probably have to redesign/layout the chip in the next technology node (say 32nm which may have lots of different non-compatible features and take lots of effort like a new high-k gate dielectric).