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IBM and AMD Create First 22nm SRAM Cell
arcticstoat notes an announcement from IBM that, along with technology partners, they have produced the first working sample of a SRAM cell built on a 22nm fabrication process. According to the article, this represents the next generation after 32nm process chips and won't be in products for some years. "The technology was developed with several partners, including AMD, Toshiba, STMicroelectronics and Freescale, as well as the College of Nanoscale Science and Engineering, where IBM performs a lot of its semiconductor research. IBM says that the cell's development involved 'novel fabrication processes,' including high-NA immersion lithography..., high-K metal gate stacks, extremely thin silicide, damascene copper contacts, and advanced activation techniques."
apple uses intel processors so we should hate amd and ibm.
Well, a single silicon atom has a radius of 110pm. I assume silicon dioxide molecule is ~500pm, which is something like 40X smaller than the 22nm process.
However, silicone dioxide is not perfectly stable and can "leak", as far as I understand it, which limits the process somewhat.
Again, assuming you need something 100X larger area-wise, you're looking at maybe a factor of 4X remaining until the process can't be shrunk any further.
But I am not an engineer.
New manufacturing processes are typically tested by producing SRAM cells, because they're a relatively typical structure and big arrays of SRAM cells are easily tested to measure the defect rate.
Like when a clown kills itself.
It doesn't mean much now, it's built for the future.
In other news IBM and AMD have hired linguists to invent new words for this process. "silicide, damascene copper contacts, and advanced activation techniques." seemed far to cool to saddle with the brand- name of the new "Blubberon(TM)" and "Humpderon(TM) processor line.
You need to think before mouthing off in ignorance.
Silicides are silicon based compounds, eg Copper Silicide, Cu_5 S. The high purity of the Si used by IBM etc means that the formation of Silicides in their samples is unlikely to come from impurities in the wafers (Fe, Co, Ni and other transition metals are generally the worst offenders). So they are most likely to form at Si-stack interfaces after annealing (essentially baking) their samples (chips).
Damascene copper is contacts are small interconnects made in multi-step stages.
1.There's a lithography step (patterning & chemical wet-etch) to make trenches for the copper connects.
2.Followed by either electrochemical deposition, or sputtering of the copper.
3.Finally after an etch/polishing step you have your connects.
"advanced activation techniques" refers to modifying the surface of the silicon wafer, and/or deposited layers on the silicon to increase deposition rate, and current efficiency. In the case of electrodeposition, you need to aim for a current efficiency of more than 10% (as in, for a given applied potential, measured current/charge, how much metal has been deposited compared to what you would expect). An electrochemist working in industry would be able to give a much more accurate value than this.
It's all a lot more complicated than this, and optimising each step is a painstaking process, and yes IAAPBOWIMSNSP (I am a physicist, but one working in magnetic systems not semiconductor physics), but that is the general gist of it.