IBM and AMD Create First 22nm SRAM Cell

arcticstoat notes an announcement from IBM that, along with technology partners, they have produced the first working sample of a SRAM cell built on a 22nm fabrication process. According to the article, this represents the next generation after 32nm process chips and won't be in products for some years. "The technology was developed with several partners, including AMD, Toshiba, STMicroelectronics and Freescale, as well as the College of Nanoscale Science and Engineering, where IBM performs a lot of its semiconductor research. IBM says that the cell's development involved 'novel fabrication processes,' including high-NA immersion lithography..., high-K metal gate stacks, extremely thin silicide, damascene copper contacts, and advanced activation techniques."

Comments

cool

[Anonymous Coward]

now if AMD could get their 45nm yeild above, say, zero percent, they'd be rockin!

When will it stop?

[4D6963]

22 nm?? Aren't we dramatically approaching the theoretical limit? What is the theoretical limit by the way?

Re:When will it stop?

[TheMeuge]

Well, a single silicon atom has a radius of 110pm. I assume silicon dioxide molecule is ~500pm, which is something like 40X smaller than the 22nm process.

However, silicone dioxide is not perfectly stable and can "leak", as far as I understand it, which limits the process somewhat.

Again, assuming you need something 100X larger area-wise, you're looking at maybe a factor of 4X remaining until the process can't be shrunk any further.

But I am not an engineer.

Re:When will it stop?

[wizardforce]

Aren't we dramatically approaching the theoretical limit?

yes.

What is the theoretical limit by the way?

for Silicon it's probably around 10nm or so. as for what is thought to be possible, molecule size components measuring a few nm.

Re:When will it stop?

[cyfer2000]

22nm could be the limit of bulk planar CMOS device, next step maybe 16nm finFET. See this for more information.

Re:When will it stop?

[rahvin112]

Assuming of course that there is no advance in technology.

I remember when they said 90nm was the limit of lithography. All the limits fall as there is a massive amount of money going into systems and methods to cheat the "limit". The real physical limit is a single atom width, at that point you can't go smaller, assuming there is a limit other than that single qualifier is dishonest because as with most of the other limits we have found ways to engineer around the "limit". Even if you think there is no way we could possibly have single atom paths you aren't considering the engineering advancement that could make such a thing possible including the use of materials other than silicon.

Re:When will it stop?

[Intron]

Yes. At 5E-09 Volkswagens we are indeed close to the limit which is one nano-wagen (nVW).

The limiting factor these days is the ability to form the circuit designer's personal logo out of individual copper atoms, however advances in X-ray lithography may reduce that limit.

Re:When will it stop?

[x2A]

I think the limits we're hitting at the moment are not so much due to the material we're cutting into, but the light we're using to do so. To cut finer we need narrower wavelength (=higher energy) light. We're already hitting the very high end of the ultra-violet spectrum (around 10nm) and approaching x-ray light. As the wavelength decreases, all sorts of other things start to change. Materials the used to reflect the light now start letting photons through, lenses no longer have any effect etc, so new ways have to be found to control light at higher frequencies.

But even here there are ideas to get around the problems, such as using quantum effects like creating interference patterns (I believe I read recently, but don't quote me on it) to cut details finer than the wavelength of the light.

Re:When will it stop?

[jeremypv]

To go smaller will take nanotechnology (perhaps carbon nanotubes)

that's the only time we can say that the internet goes to a series of tubes

Re:When will it stop?

[blind biker]

I don't mean to be offensive, but almost all those numbers are just pulled from your ass (and I am sure you'll agree).

For the record, today exist technologies for depositing atomic monolayers of various oxides and even elements. Also, if you think of it, CNTs are nothing more than graphene cylinders - therefore, a carbon atom monolayer.

Furthermore, CMOS transistors with 17nm long gates have been fabricated already in the distant 2006. Planar CMOS with gates of 15nm have been fabricated in "prehistoric" 2001! And if you think that is impressive, check out this article from the even more distant past

So, 22nm is far from a physical limit, which is a statement easily demonstrated - by historical events, so to say.

Re:When will it stop?

[delibes]

I did study electronic engineering, but it was 14 years ago and I'm not sure my answer's much better ...

A popular on-line encyclopaedia says that Silicon has a Van der Waals radius (the size if we pretend the atom is a solid sphere) of 210pm - over 100 times less than the 22nm process. If you also count the need to dope the silicon p-type or n-type, grow layers of insulator like silicon dioxide and avoid quantum stuff that I never really understood, then I'd guess at a lower limit of around 25 or so atoms for a workable structure. Let's call it 5nm - hey that's a factor of 4x less than 22nm like you said!

From a different point of view, I've seen papers by groups who have been fabricating structures at the sub-10nm region. Again, perhaps it can be pushed to 5nm.

Beyond that we'll need to think about alternatives - making electrons move faster, like strained silicon does, or giving up silicon for something like diamond (so we can have super-computer bling :)

If the silicon process shrinks every 2-3 years, we'll hit the limit about 10 years. But they said that 10 years ago too!

Re:When will it stop?

[iris-n]

This "quantum stuff" you talk about is probably tunnelling, which will make electrons leak the transistors if they are too small.

The exact distance is hard to tell, but in my STM I use around 10 angstroms (fuck ASCII), to get a sizeable current through a potential wall. So, I bet that 20 angstroms would suffice to make it negligible, and so, accounting for other instabilities, I would agree with parent in 5 nm.

Re:IBM and AMD

[XanC]

Morgan Freeman? Is that you?

Remember

[Anonymous Coward]

apple uses intel processors so we should hate amd and ibm.

Re:Remember

[x2A]

But IBM put money into linux/oss development (*cheers*) and they fought SCO (*boo's*) who hate so that makes them good... but they also built machines for the nazi's (*boo*) but cuz of the whole nazi thing we have Fanta (*...erm... do we like fanta?*). AMD + ATI = open source graphics drivers (*yay*) but Intel = open source graphics drivers all by themselves (*bigger yay*). IBM, even if they did get shat on during the process, are kinda responsible for putting MS (*smashes bottle and puts broken sharp pieces to its neck*) where it is now.

Erk... I think I'm going to need to have to create some kinda graphical relationship manager for this one, create a love/hate score for everyone involved, in the same way Google create pageranks, and I'll get back to you on whether we do in fact love or hate IBM or not. Stand by...

In case you're wondering why SRAM...

[Anonymous Coward]

New manufacturing processes are typically tested by producing SRAM cells, because they're a relatively typical structure and big arrays of SRAM cells are easily tested to measure the defect rate.

Re:In case you're wondering why SRAM...

[warrior]

They're also usually made from _the_ smallest transistors on the die for density reasons. Aside from being able to print these features you also need to reliably set the threshold voltages of all the transistors to make a cell that is both writeable and read-stable. This is not easy to do. For the FET sizes involved in this cell you're probably looking at only tens of dopant atoms setting the Vt. It only takes a few more or a few less dopants to really shift the Vt of said device which could push it into a point where you either can't write the SRAM cell or it flips when you try to read it. Once a process is reliably yielding good SRAMs it's usually "ready to go".

FFS!

[ZarathustraDK]

The more I pay the less I get! What have the world come to?

Re:IBM and AMD

[Anonymous Coward]

In other news IBM and AMD have used words I don't know

Is that what you meant to say?

Silicide. Damascene. And have you never heard of a Damascene conversion?

Ah, Silicide

[Pope]

Like when a clown kills itself.

Re:IBM and AMD

[vigour]

In other news IBM and AMD have hired linguists to invent new words for this process. "silicide, damascene copper contacts, and advanced activation techniques." seemed far to cool to saddle with the brand- name of the new "Blubberon(TM)" and "Humpderon(TM) processor line.

You need to think before mouthing off in ignorance.

Silicides are silicon based compounds, eg Copper Silicide, Cu_5 S. The high purity of the Si used by IBM etc means that the formation of Silicides in their samples is unlikely to come from impurities in the wafers (Fe, Co, Ni and other transition metals are generally the worst offenders). So they are most likely to form at Si-stack interfaces after annealing (essentially baking) their samples (chips).

Damascene copper is contacts are small interconnects made in multi-step stages.
1.There's a lithography step (patterning & chemical wet-etch) to make trenches for the copper connects.
2.Followed by either electrochemical deposition, or sputtering of the copper.
3.Finally after an etch/polishing step you have your connects.

"advanced activation techniques" refers to modifying the surface of the silicon wafer, and/or deposited layers on the silicon to increase deposition rate, and current efficiency. In the case of electrodeposition, you need to aim for a current efficiency of more than 10% (as in, for a given applied potential, measured current/charge, how much metal has been deposited compared to what you would expect). An electrochemist working in industry would be able to give a much more accurate value than this.

It's all a lot more complicated than this, and optimising each step is a painstaking process, and yes IAAPBOWIMSNSP (I am a physicist, but one working in magnetic systems not semiconductor physics), but that is the general gist of it.

Re:IBM and AMD

[Bender_]

Almost...

Silicides are used to create low resistivity contacts to doped silicon. Typically a metal is deposited on the wafer surface and then heated to react with the crystalline substrate to form the silicide. Commonly used silicides are NiSi, CoSi and TiSi.

You got the copper right. The here appears to be that they are using copper down to the silicon substrate. Copper does easily "poison" the electrically active regions and is hence typically only used in higher level wiring layers. Getting it down to the silicon is challenging.

The advanced activation techniques refer to thermal processing steps that are used to incorporporate N and P dopants into the crystal lattice. The challenge here is to heat the wafer to above 1000C within seconds. IBM is probably a laser or flash lamp process for this.

Re:IBM and AMD

[vsny]

Thank you, that makes more sense.

However, isn't a flash lamp (RTA) the standard process?