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IBM Leapfrogs Intel With 22nm Chips
Slatterz writes "Intel may be touting 45nm CPUs, but IBM says it can go much further with a strategy to produce future chips using a 22nm fabrication process. The company is adopting a technique called 'computational scaling' in order to manufacture circuits small enough to deliver more powerful and energy-efficient devices. Intel plans to introduce 32nm chips in 2009, but chipmakers have hit a problem in that current lithographic methods are not adequate for designs as small as 22nm owing to fundamental physical limitations. IBM claims to have solved this problem." Unfortunately the phrase "computational scaling" doesn't actually convey any information about how they've solved it.
FTFA: "IBM said that computational scaling overcomes these limitations by using mathematical techniques to modify the shape of the masks and the characteristics of the illuminating source used to image the circuits for each layer of an integrated circuit."
That gives you an idea. They are not being more secretive than normal.
"Civis Europaeus sum!"
Via their press release: http://www-03.ibm.com/press/us/en/pressrelease/25147.wss
IBM and Intel have complete cross-site patent agreements. Anything that IBM patents in the future, Intel already has a license for -- and vice versa. Trade secrets, on the other hand, are legally protected as long as the company with the secret takes adequate steps for it to remain a secret.
Most users are just fine with a fixed system on a chip with no PCI. (ram too if you could pull that off) If you want to reduce power and cost you'd place as much as possible on a single chip.
Chips like TI's OMAP series (found in the Nokia handhelds, OpenPandora, and a load of other things) have a CPU, DSP, GPU and a load of other things in the same die. They use a stacked-chip design so you can plug 128MB of RAM (256MB coming soon) on top of the package. Power usage is around 250mW.
How about a working variation of Hyperthreading?
Hyperthreading is a Intel's implementation of an idea that IBM brought to market first (based on an academic research project which produced the first prototypes, with the original designer now working at Sun). Sun and IBM have had it working for years. As have a few others. Unlikely in ARM chips, since the performance/power benefits in this space are worse than with multi-core (Cortex A9 allows up to 4 cores). It only makes sense for Intel in the Atom because it allows two context to share an instruction decoder, which reduces the cost of x86 bloat a bit.
How about hardware accelerated stacks?
x86 chips have had hardware accelerated stacks for well over a decade - rewrite an iterative algorithm with a software stack as a recursive implementation and you'll see a speedup.
MMUs that can handle a driver memory space
IOMMUs have been in Sun and IBM chips since they introduced 64-bit CPUs and wanted to plug in 32-bit PCI devices. Newer Intel and AMD designs also include them.
Advances in clockless processing?
Asynchronous designs have been floating around for a few decades but still don't deliver the kind of performance benefit that offsets the extra complexity (which equates to extra power usage).
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