Intel Details Upcoming Gulftown Six-Core Processor
MojoKid writes "With the International Solid-State Circuits Conference less than a week away, Intel has released additional details on its upcoming hexa-core desktop CPU, next gen mobile, and dual-core Westmere processors. Much of the dual-core data was revealed last month when Intel unveiled their Clarkdale architecture. However, when Intel set its internal goals for what its calling Westmere 6C, the company aimed to boost both core and cache count by 50 percent without increasing the processor's thermal envelope. Westmere 6C (codename Gulftown) is a native six-core chip. Intel has crammed 1.17 billion transistors into a die that's approximately 240mm sq. The new chip carries 12MB up L3 (up from Nehalem's 8MB) and a TDP of 130W at 3.33GHz. In addition, Intel has built in AES encryption instruction decode support as well as a number of improvements to Gulftown's power consumption, especially in idle sleep states."
Can most programmes really be written to take advantage of so many cores? I am not sure I want to have a 6-core processor, of which 5 spend most of the time idling as I am only running a single-core-aware programme. OK, one more core can be used by the OS to make everything snappy, but the question stands.
not
Perhaps a jump in number of cores will convince people outside the Apple and FreeBSD camps to port Grand Central Dispatch.
Letting the kernel team handle the hairier parts of multi-threaded design should make it easy for barely-optimized software to use powerful hardware.
Could its Apache license work with the #1 OS family?
I'll be your candy shop of infinite deliciousity if you'll be my discotheque of endless rump-shaking.
1.17 billion transistors into a die that's approximately 240mm sq
That's a big chip.
we see things not as as they are, but as we are.
-- anais nin
Talked to our HP rep a few weeks ago about them. As soon as HP ships proliant servers with the new CPU's, we're going to buy 4 of them. Just haven't decided if we're going with 36GB RAM or 72GB RAM. 72GB RAM is only $2000 more than 36GB RAM these days.
Just so you know, I made this joke almost two years ago:
http://hardware.slashdot.org/comments.pl?sid=465898&cid=22548916
They could have gone to 3 cores, like the competition. That seems like the logical thing to do, but they said "Fuck it, we're going to six". What part of this don't you understand? If two cores is good, and four cores is better, obviously six cores would make them the best fucking CPU that ever existed.
http://www.theonion.com/content/node/33930 [theonion.com]
/I'm just waiting for the day Intel says "this one goes to 11"
It's the CPU joke that will never die.
[Fuck Beta]
o0t!
You can bet the sole reason for including this was to support DRM-protected content.
first
looks like you need more cores
So I skimmed TFA (gasp!) and it appears that Intel is finally following AMDs lead by keeping thermal envelopes constant.
I note that this is still a effectively 2 CPUs with 3 cores each, but that's better than legacy Intel approaches, which would have been 3 sets of dual cores.
It will be interesting to see how independent performance benchmarks play out between the new processors that are coming out.
The cesspool just got a check and balance.
blah blah Beowulf blah blah
1.17 Billion transistors. Anyone remember the 6502, the 6800, and then the 68000? 68K transistors was a LOT in 1980 and made for a fantastic 32bit architecture. Now we're at 17000 times that count. Sometime you just have to stop for a moment and think just about the numbers.
Instead of churning out cores they schould tweak the x86 isa to use multiple cores efficently. 1/2-word Atomic compare and swap is not enough, you cannot make atomic lockless doubly linked lists with that. No wonder something as interesting as http://valerieaurora.org/synthesis/SynthesisOS/ is not possible on x86 without major hacks.
"Most programs are very much not written to take advantage of multi-cores." - by physburn (1095481) on Thursday February 04, @08:56AM (#31021596) Homepage
They don't have to be, man. Why?
Well - That's because as long as the program is multithread design, the OS kernel mode process schedulers in today's modern OS' take care of sending parent or child threads of processes to the least saturated CPU cores available, & especially if the other ones are 100% used up, available cpu-cycles-wise, and no "# of processors or cores available" checking code required!
(Code in API calls like "SetThreadAffinity" or "SetProcessAffinity" for explicitly directed "cpu core directed code" are not really required either actually, because of today's process schedulers in modern OS' like Windows 7 & others (though it's not a bad idea for "extra levels of control", albeit @ the application level, rather than depending on the OS process scheduler subsystems)).
In fact, since you stated that, & I stated what I have now??
Well... take a peek @ your Taskmgr.exe (with the processes tab open & the threads column selected + viewable)...
You'll probably see pretty much as I do here, and, as I have for YEARS now no less: That most of the processes running on your system now have 2-N threads running PER PROCESS already (making them inherently mult-CPU/multi-CORE ready, because of the design of today's modern OS' process scheduler subsystems + multithreaded code design).
APK
P.S.=> As an E.G.-> Here, I have a total of 34 processes running. Every one of them has AT LEAST 2 threads no less!
Again - Thus, every one of them is "multicore/multicpu" ready in essence, & they do take advantage of them due to modern OS process scheduler kernel mode subsystems design (& MS putting in completion ports to get over "spinlocks" usage allows Windows 7 to scale very well above & beyond even 16++ cpu cores, & iirc, up to 256 or more)... apk
Why put AES on-board? I thought AES was relatively fast as encryption algorithms go. Plus, it is inevitable that AES will be replaced at some point, so why include something so specific in a chip now? It will suck to have to implement that in the processor in 20 years when nobody uses AES any longer. This is the whole point of a processor - include generic instructions that are useful for implementing any algorithm.
>Westmere 6C (codename Gulftown)
Really? I fricking hate codenamed codenames...
Wow... looks like the AMD fanboys are modding up anything anti-Intel today!
So for the past 5 years it's been a big deal to improve power consumption and everyone in the industry has known this... so all of the sudden Intel is "copying" AMD by making a CPU that fits into existing power envelopes on existing platforms???? The only "copying" going on here is marketing BS. Oh since AMD's own 6-core server CPU's came out after Intel's (Dunnington was out first) and AMD's 6 core desktop parts will come out after Gulftown will you say "yawn, AMD is just copying Intel's idea"? Somehow I think not.
Face it, AMD on the CPU side only beats the Core 2 by clocking higher and selling at a loss right now. Bulldozer had better beat the ever loving crap out of Westmere because by the time it finally arrives late next year it's going to have to contend with Sandy Bridge.
The only bright spot at AMD is the graphics division... which AMD just bought for way too much money and likely will require massive profits for the next 10 years to recoup the takeover prices.
AntiFA: An abbreviation for Anti First Amendment.
In the server space we've gone through the same thing. Sun introduced the T1 with 8 cores and 32 threads (now 64 on T2). Lots of software wasn't suitable for this type of horizontal scaling. But over a period of five years, that changed dramatically.
On the desktop, you can expect the same. For now, not many desktop apps will take advantage of the additional cores. But if Intel would have stuck with 1-2 cores, no software will be written to take advantage of multiple cores.
Chicken or egg ....
Browsers shouldn't have a back button!! It's all about going forward...
I note that this is still a effectively 2 CPUs with 3 cores each
You need to skim a little slower. It is a single die, native six core chip. From the article:
Westmere 6C (codename Gulftown) is a native six-core chip
Yes, some functional blocks are "split in two" and assigned to three cores. Those blocks are split up because it makes engineering sense to do so, not because the designers were lazy or "slapped together" two non-six core designs.
If you look at a GPU with 10's or 100's of cores you will see that some functions are "split up" with each piece being assigned to (and located close close by!) some subset of cores. That does not make them "effectively X number of CPU's."
"Liechtenstein is the world's largest producer of sausage casings, potassium storage units, and false teeth."
I'm pretty sure it is one die, with communication possible between any cores. It just looks like 2x3 due to the way it is laid out.
... is the number!
This comes the same month as the release of 16-core processors by IBM and Oracle, and a 12-core from AMD. This isn't that impressive.
with an AMD X3 Core 2 Duo or AMD X3X2...
Though I wonder why we are going to 6 rather than 8. Core 2 Quad Duo's? Head 'esplodes....
I just can't wait till the Quad Quads... or something spiffy, like Quad Squared. 16 is probably a ways off from the consumer market anyway.
It's a monolithic *native* 6-core design... not two sets of three, or three sets of two... it's ONE set of 6 cores... sheesh... AMD is stealing an OLD page from Intel's playbook using a multi-die MCM approach - that is so yesterday...
Having 6+ cores is a complex issue for the desktop. In the 'olden' days it way easy to do the math that per Mhz, the less cores the faster ( a pair of 1Ghz chips is slower than a 2Ghz CPU if all all other things are equal)
But now, each CPU can have a dedicated memory bus. That means that 2 cores can be FASTER than a single core because 2 cores can have twice the memory bandwidth. Its not necessarily about clock cycles but bandwidth.
More cores also can improve the desktop experience. because flash is currently stuck on a single CPU, your system cant get totally rocked by flash. If you have a really intense process, you could set the CPU affinity to 5 of the 6 cores to make sure you had one left over. The process scheduler should try to do this on its own but its not always successfull.
I run some VM hosts on dual quad cores and processor affinity for virtual machines is very important. On one box I have CPUs that are 2 dual cores on a single CPU and then 2 sockets. A VM on CPU1&2 (numerically 1-8, not 0-7) is ideal. A VM on 2&3 is slow and a VM on 4&5 is rediculously slow because you go from a signle chip, to two chips, then to a core on seperate sockets. This is an extreme case but it is true on the desktop as much as it is anywhere else.
Any high transaction count server that runs multiple processes or threads will make very good use of 6 cores as these process tend to not jump between cores ( or shouldnt if the programmers are concerned about performance)
24 x86 cores just doesn't compare to 1 Fermi with 512 striped down vector processors
CPU hogging programs can be a real pain, especially on a multi-user system. I know of businesses that run keyboard polling applications on a Terminal Server, for example. Each instance easily pin a core at 100%.
If you ever run into a problem like this (on Windows), check out ThreadMaster
I read the article. Where were the Hexa core details ?
Or a game boy or something like that. Of course you would have to wear asbestos gloves to play with the thing... :)
It's a shame they didn't make a mid-level version with no graphics core, a la Core i7 860. As a crypto/security guy, I'd like to try out PCLMULQDQ, the AES instructions and maybe the IOMMU. But if I'm going to get a fancy new computer, I might as well put a decent graphics card in it, at which point their on-die graphics card is simply a waste of space, power, money and latency. And no, I'm not dropping $1k for a 6-core Gulftown.
I hereby place the above post in the public domain.
I'm running 2.6.32 with the fabulous new scheduler and all those "low latency" settings painstakingly compiled in. Nevertheless, I'm currently making some DVD isos and while mkisofs is running, firefox has to think for five or six seconds before loading every page. Somehow I doubt that having two extra cores is going to help me here...
Right. When's AMD's native 6 core processor out, again? Oh, I forgot.. they don't have the process technology to make such a thing, only Intel does.
"which would have been 3 sets of dual cores."
The have been previous intel hex-core processors which were three dual-core dies in one package.
This is one die though it does seem to have two seperate L3 caches. feeding off a central memory controller and queue (with the two QPI interfaces on the other end of the L3 caches).
note: i'm known as plugwash most places but i screwd up registering that here somehow in the past and now can't register
It was announced in Oct. It has a single shared L3 cache. Anon Intel fanboy? Whatever for? Embarrassed?
The cesspool just got a check and balance.
"Jesus Christ APK, you're useless." - by metrix007 (200091) on Thursday February 04, @01:31PM (#31025064)
See subject-line above, & prove me incorrect is all!
(OH: Please also see my 'P.S.' below, as to my being "useless"... & "argue with the numbers", ok?)
APK
P.S.=> If I am "so useless", then how did all of these happen then?
"My Name is Ozymandias: King of Kings - Look upon my works, ye mighty, & DESPAIR..."
----
Windows NT Magazine (now Windows IT Pro) April 1997 "BACK OFFICE PERFORMANCE" issue, page 61
(&, for work done for EEC Systems/SuperSpeed.com on PAID CONTRACT (writing portions of their SuperCache program increasing its performance by up to 40% via my work) albeit, for their SuperDisk & HOW TO APPLY IT, took them to a finalist position @ MS Tech Ed, two years in a row 2000-2002, in its HARDEST CATEGORY: SQLServer Performance Enhancement).
WINDOWS MAGAZINE, 1997, "Top Freeware & Shareware of the Year" issue page 210, #1/first entry in fact (my work is there)
PC-WELT FEB 1998 - page 84, again, my work is featured there
WINDOWS MAGAZINE, WINTER 1998 - page 92, insert section, MUST HAVE WARES, my work is again, there
PC-WELT FEB 1999 - page 83, again, my work is featured there
CHIP Magazine 7/99 - page 100, my work is there
GERMAN PC BOOK, Data Becker publisher "PC Aufrusten und Repairen" 2000, where my work is contained in it
HOT SHAREWARE Numero 46 issue, pg. 54 (PC ware mag from Spain), 2001 my work is there, first one featured, yet again!
Also, a British PC Mag in 2002 for many utilities I wrote, saw it @ BORDERS BOOKS but didn't buy it... by that point, I had moved onto other areas in this field besides coding only...
Lastly, being paid for an article that made me money over @ PCPitstop in 2008 for writing up a guide that has people showing NO VIRUSES/SPYWARES & other screwups, via following its point, such as THRONKA sees here -> http://www.xtremepccentral.com/forums/showthread.php?s=ee926d913b81bf6d63c3c7372fd2a24c&t=28430&page=3
(That last one's also featured here as one of your "ESSENTIAL GUIDES" -> http://www.neowin.net/forum/index.php?s=ded3dfdba4dba2091d4d73d674bbfdf6&showtopic=602537 )
----
What do I have to say about that much above? I can't say it any better, than this was stated already (from the greatest book of all time, the "tech manual for life" imo):
"But by the grace of God I am what I am: and his grace which was bestowed upon me was not in vain; but I labored more abundantly than they all: yet not I, but the grace of God which was with me." - Corinthians Chapter 10, Verse 10
(And, because I got LUCKY to have been exposed to some really GREAT classmates, professsors, & colleagues on the job over time as well)
apk
"Most threads spend most of their time blocked waiting for some kind of event, while occasionally doing some quick action in response and then blocking to wait for an event again." - by petermgreen (876956) on Thursday February 04, @03:56PM (#31026852) Homepage
If they run on the same data & on the same CPU core? Possibly... but, not always: It depends!
Say, In the case of "coarse multithreading" - where 1 thread works on 1 set of data, which is independent of another thread of execution working on another in the SAME APPLICATION no less!
(E.G.=> Where say Thread #1 is recalc'ing a few cells in a spreadsheet, AND, while another Thread #2 is printing another worksheet from said spreadsheet? Not likely to "blockout" one another via mutexes/semaphores etc. et al, because the data being worked on is different, so the threads can continue execution, concurrently, because the dataset being worked on by both threads IS independent of the other dataset).
Now, in a situation like this one:
A = B+D (thread #1)
C = A+B (thread #2)
You'd be correct - because C has to "wait out" the operation on A to complete, first.
----
"The number of tasks doing serious processing work is usually in the range 0-1 unless you either start multiple intensive tasks at once or you have software that is specifically designed to take advantage of multiple processors/cores." - by petermgreen (876956) on Thursday February 04, @03:56PM (#31026852) Homepage
I think you should read up more on today's PROCESS SCHEDULING KERNEL MODE SUBSYSTEMS, first... & SECONDLY, on the diff. between "coarse multithreading" vs. "Fine grained multithreading" (this latter one is nearly the opposite of the one I explained above, & more like the math example I put up (where threads work on the same data, & sometimes/more often? There, you do get "blocking", a lot more often)).
APK
P.S.=> "NEXT"... that's to ALL THE TROLLS around here, lol... "bring it on boys"... apk
"Jesus Christ APK, you're useless." - by metrix007 (200091) on Thursday February 04, @01:31PM (#31025064)
Well, per my subject-line above, & yet more of the same in my other reply to that quote of YOURS above -> http://hardware.slashdot.org/comments.pl?sid=1536394&cid=31029376
?
Others seem to disagree, quite strongly.
Well, yet more for you to read while you "eat your words" quoted above:
====
+5 'modded up' posts by "yours truly" (4):
http://it.slashdot.org/comments.pl?sid=1139485&cid=26975021
http://it.slashdot.org/comments.pl?sid=1139485&cid=26974507
http://it.slashdot.org/comments.pl?sid=170545&cid=14210206
http://hardware.slashdot.org/comments.pl?sid=175774&cid=14610147
----
+4 'modded up' posts by "yours truly" (4):
http://slashdot.org/comments.pl?sid=161862&cid=13531817
http://developers.slashdot.org/comments.pl?sid=167071&cid=13931198
http://tech.slashdot.org/comments.pl?sid=1290967&cid=28571315
http://tech.slashdot.org/comments.pl?sid=1461288&cid=30273506
----
+3 'modded up' posts by "yours truly" (5):
http://developers.slashdot.org/comments.pl?sid=155172&cid=13007974
http://it.slashdot.org/comments.pl?sid=166850&cid=13914137
http://slashdot.org/comments.pl?sid=175857&cid=14615222
http://slashdot.org/comments.pl?sid=273931&threshold=1&commentsort=0&mode=thread&cid=20291847
http://it.slashdot.org/comments.pl?sid=1021873&cid=25681261
----
+2 'modded up' posts by "yours truly" (25):
http://it.slashdot.org/comments.pl?sid=158231&cid=13257227
http://it.slashdot.org/comments.pl?sid=1361585&cid=29360367
http://science.slashdot.org/comments.pl?sid=158310&cid=13263898
http://it.slashdot.org/comments.pl?sid=1361585&threshold=-1&commentsort=0&mode=thread&cid=29358507
http://it.slashdot.org/comments.pl?sid=158231&cid=13257227
http://slashdot.org/comments.pl?sid=290711&cid=20506147
http://slashdot.org/comments.pl?sid=245971&cid=19760473
http://it.slashdot.org/commen
watch castle
I'm not the world's leading expert on processor design, but from what I can tell from the schematics and die pictures I've seen of the Westmere 6-Core CPU's, it only *looks* like they stuck 2 3-core processors on the same die. Everything I have read about Nehalem (and now this current die-shrink) has said how modular and scalable it has been designed to be; Intel saw the limitations of their early dual-core designs in that they *weren't* particularly modular or scalable, and I can't imagine that they would repeat that mistake.
That said, from what I can tell, they laid it out like they did (so that it looks like three cores on one side and three on the other) in order to minimize the maximum distance(s) between certain key components (they stuck the queue and most of the uncore in the middle). It is my assumption that although there appears to be two L3 caches on the die, that any core can directly access any of the cache. I base this mostly on my understanding of how the QPI system works on a DP platform -- one link is for communicating with the Northbridge (Current DP NB is tylersburg 5520 while SP boards usually use X58) while the other is for direct communication with the other processor --- I would assume that if processor 0 can get data directly from the cache on processor 1, that any core on processor 1 can access any data on it's internal shared cache.
It will be interesting to see if this is borne out in the benchmarks. I'm very curious regarding these details. It'd be very nice if the #1 CPU maker was on the same playing field as the current tech of the day. We would all benefit from that situation.
The cesspool just got a check and balance.
"Most threads spend most of their time blocked waiting for some kind of event, while occasionally doing some quick action in response and then blocking to wait for an event again" - by petermgreen (876956) on Thursday February 04, @03:56PM (#31026852) Homepage
Don't you mean threads spend most of their time idling rather than blocking one another out of a requested data resource? I find that what you're using for an example of what you call blocking is not the same thing as blocking for a resource being held by another thread, blocking another thread of execution's clean access to said resource, where 2 or more threads are using the same data. What you illustrate is a program's threads of execution waiting for user inputs in event driven programming, and that is idling on a program's part, not blocking technically, as said thread of execution waits for user actions for inputs.