Toshiba To Test Sub-25nm NAND Flash

An anonymous reader writes "Toshiba plans to spend about $159.8 million this year to build a test production line for NAND flash memory chips of less than 25 nanometers. The company hopes to kick off mass production of the chip as early as 2012. The fabrication facility for this key NAND flash memory will be located at Yokkaichi, Mie Prefecture."

Comments

microSD

[Hatta]

I thought microSD was small. I'm going to lose this stuff for sure!

Re:microSD

[Stenchwarrior]

That's what they're hoping!

You forgot the "so what".

[rindeee]

Not everyone (including me) understands what the benefit to consumers will be when less than 25nm production is possible. Does that mean 1TB flash memory cards for my camera? Same sizes as now but cheaper? What? Just an additional sentence giving a "once possible, this will mean blah blah blah blah blah". Simple as that. Of course, with an 'article' (actually just PC Mag parroting a Thoshiba presser...for pay I'd imagine) as crappy as the one linked to in the headline, I don't know that it really matters.

Re:You forgot the "so what".

[digitaldrunkenmonk]

The smaller the transistors, the more that can be packed into a smaller area. Basically, this will allow you to have smaller chips that will have denser memory capacities. The benefits come into things like phones, tablet PC's, netbooks, cameras, cars, computers, etc. Anything that uses or can use digital memory will benefit from smaller components.

It'll also decrease the price for components out now, and that's always nice.

I just wonder what'll happen when we hit the quantum wall -- the point at which quantum effects become apparent and electronics behave erratically.

Re:You forgot the "so what".

[RabidMoose]

The reason this is a big deal, is that this is the type of flash that goes into SSD's. Right now, a 256GB SSD costs over $600. Read/write speeds on mainstream HDDs are one of the biggest bottlenecks in today's machines, and SSDs are the answer to the problem, once they come down in price. Also, SSDs draw less power than traditional hard drives, so longer laptop battery life is an added benefit. Not to mention the benefit that data centers could see, both from a throughput standpoint, and a lower power/cooling requirement.

Re:You forgot the "so what".

[TheRaven64]

witch means an approx 4 x larger yield on a 300mm wafer

I'm not sure what witches have to do with it, but the yield improvement from a process shrink is more than just the 4x that you get from cramming four times as many chips on a wafer. An impurity in the wafer typically destroys one die. If you're unlucky it may be between 2 or even 4. If you make each die smaller then an impurity of the same size may only destroy 1-3 of the 4 in the same area as one of the originals.

Re:You forgot the "so what".

[ThreeGigs]

Shrinking a process gives several benefits, but a quick general overview helps:
Silicon as used in chip manufacturing is expensive. It costs a lot to grow, cut and polish. It's also a mature industry, so no real breakthroughs are likely to happen to reduce the cost of the silicon. The less silicon area you use, the more chips you can make for the same cost. Next is manufacturing. Whether you put one transistor per square millimeter or 100,000 per square millimeter, the cost is the same, or at least within a penny. Coat, expose to a masked pattern, etch, sputter, clean and repeat a few times, and voila, you have a chip. Shining a light through a mask costs the same no matter the resolution of the mask. Dunking the wafer in a chemical etch bath is the same, running a wafer through a sputterer or CVD costs the same, etc. Labor costs are basically per wafer, so more components per wafer means you get more output for the same labor (and plant infrastructure) dollar.

So, a smaller manufacturing process means:
More components per wafer. Thus if you double the component density, your manufacturing costs will remain the same, and you can double output while keeping costs the same (think 32GB for the price of 16GB).

You can also make the chips smaller while keeping the same capacity (same 16GB chip uses half the silicon, thus costs 50% less to make, think 16GB for half the cost you paid last year).

Or, more capacity within given size limits. (think 64GB or 128GB SD cards, or 2 TB Compact Flash).

Re:You forgot the "so what".

[marcansoft]

MLC NAND Flash is already horribly unreliable. Manufacturers don't care about errors, quantum or not. The proper question to ask is when will quantum effects become dominant such that decreasing feature size loses more memory from failure than you gain from the reduced size. Until then, people will just slap on better ECC and nobody cares if a large number of bits are randomly flipping.

When does it stop?

[RulerOf]

Over the last decade, I keep seeing these manufacturing processes grow ever smaller. I still remember when I bought my Athlon FX-55. 130nm process. Aw hell yeah. It's currently living the remainder of its life in one of my guest boxes. God that chip was such a waste of money, but I digress.

For those in the know, this ever shrinking manufacturing process tech: when will it stop? Where will it stop? 10nm? Sub-1nm?

Re:When does it stop?

[blackraven14250]

*tronics

Chemitronics? Quantatronics? What does this mean?!?!?

Re:Marginal Gain?

[Anonymous Coward]

Well, chips are 2D, so you also get to square that benefit.

32x32 = 1024 nm^2
25x25 = 625 nm^2

That's nearly 18 months of Moore's Law right there.

ultimate limit

[goombah99]

Is there a proposed ultimate limit for lithography before one has to jump to molecular electronics? 25nm is well below what anyone though practical a decade ago (since it's so many times smaller than easily produced optical wavelengths). Now it's closing in on the limit of easily produced x-rays.

while the resolution of the smallest resolvable element is shrinking, is the utilization of area increasing proportionally. That is are we densely filling the area with 25nm structures or is that simply the finest linear element and these are well separated?

A 1cm chip would have 1E15 resolvable points at 0.025 micron resolution. And then there is the vertical resolution to multiply that. I should think it would become prohibitively difficult to design something with so many possibilities.

Re:ultimate limit

[RabidMoose]

Actually, it looks like the answer is going to be to step away from silicon, and replace it with graphene. They can't make it anywhere near as small as silicon (yet), but there's other advantages. The linked article is a pretty good primer on the subject.

Re:ultimate limit

[vlm]

Hmm. Well, Si unit cell spacing is about 0.5 nm and graphene C-C spacing is about 0.15 nm. The longest diagonal of a hexagon is twice one side, so the minimal graphene unit cell lattice would be about 0.30 nm.

So, for all the trouble of scrapping an entire industry and starting over, we'd only go from 0.50 to 0.30 nm. Not sure if thats going to be worth it.

Not that graphene isn't interesting or cool, just that its unit cell isn't much smaller than Si unit cell.

What would this mean for the consumer?

[Firethorn]

Personally, while I find it interesting, I'd like to know just how much extra data storage this would enable?

32nm to 25 nm would, what, increase the theoretical max density of flash by 64%? IE instead of getting a 16GB chip you'd get a 24GB one.

At the same price once you have all the details worked out, of course.

45nm to 25 nm by my figuring would allow 3.24 times as much storage in a given size of chip.

Re:NAND?

[AdamHaun]

No, it has little to do with the NAND digital logic gate -- the other person who responded to you is totally wrong. NAND flash is a circuit topology where the flash transistors (bits) are arranged in long series chains, like this:

http://commons.wikimedia.org/wiki/File:Nand_flash_structure.svg

which is similar to the pull-down side of a NAND gate. NAND flash is very high-density but is read in blocks (you turn on the whole chain and then check one bit at a time). The other type of flash is NOR flash, which uses transistors in parallel:

http://commons.wikimedia.org/wiki/File:NOR_flash_layout.svg

This means you can read any bit individually without having to turn the others on. NOR flash is commonly used for program memory in microcontrollers, where you need fast random access to any bit. NAND flash is used when you need high capacity, as in memory cards or SSDs.

Details?

[AdamHaun]

The article is frustratingly light on details. There's nothing about what type of flash transistor they're using (there are several variants on the basic stacked-gate NMOS design as well as more wild types). They don't say whether they're actually shrinking the bits (which you don't have to do) or just the support circuitry. All it says is that Toshiba is making NAND flash in a new process node, probably 22nm.

My day job is working with embedded NOR flash. I'm not really a process or solid state physics guy, but I think I know enough to comment, unlike a lot of the people running their mouths. (Seriously, folks, if you don't know what you're talking about, *shut up*. Misinforming people with wild guesses is not helpful, no matter how much it strokes your ego.)

First off, the flash transistor itself is not 22nm long. It's probably at least ten times longer, if not more (obviously Toshiba's not giving exact numbers). When you go to a new process node you don't necessarily shrink every feature by 50%. The limiting factor in flash size isn't lithography (manufacturing), it's leakage.

Flash works by storing electrons on an isolated (floating) material sandwiched inside an NMOS transistor. If extra electrons are present, the transistor is forced off (0). If they aren't, the transistor can turn on (1). The problem is that over time the electrons leak out of the floating gate, eventually causing bits to flip. If you shrink the circuit enough you hit a point where you can't keep electrons in the gate for a reasonable amount of time. At that point, we'll need a new memory technology -- maybe FRAM, maybe something else. Whatever it is, I'm sure it's been researched already -- a lot of the major research papers for flash memory are 25+ years old.

Also, I said this elsewhere, but NAND flash is called NAND because the flash transistors (bits) are in series, like the NMOS transistors in a NAND gate. It isn't made out of logic gates or anything like that. Flash memory is analog, like DRAM -- you need special analog circuitry to read it and output a digital signal.