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How Much Smaller Can Chips Go?
nk497 writes "To see one of the 32nm transistors on an Intel chip, you would need to enlarge the processor to beyond the size of a house. Such extreme scales have led some to wonder how much smaller Intel can take things and how long Moore's law will hold out. While Intel has overcome issues such as leaky gates, it faces new challenges. For the 22nm process, Intel faces the problem of 'dark silicon,' where the chip doesn't have enough power available to take advantage of all those transistors. Using the power budget of a 45nm chip, if the processor remains the same size only a quarter of the silicon is exploitable at 22nm, and only a tenth is usable at 11nm. There's also the issue of manufacturing. Today's chips are printed using deep ultraviolet lithography, but it's almost reached the point where it's physically impossible to print lines any thinner. Diffraction means the lines become blurred and fuzzy as the manufacturing processes become smaller, potentially causing transistors to fail. By the time 16nm chips arrive, manufacturers will have to move to extreme ultraviolet lithography — which Intel has spent 13 years and hundreds of millions trying to develop, without success."
Make them bigger. More space to put stuff on them then anyway. Tostito's Restaurant style tortilla chips can fit much more guacamole and salsa on them than their bite size chips. Bigger is better when it comes to chips.
They're going to hit atomic scale transistors fairly soon from what I can see as well, the manufacturing process for those is probably prohibitively expensive but that is as small as they can go(according to our current knowledge of the universe at least).
I can't imagine Intel has all of its eggs in one basket on Extreme Ultraviolet Lithography though. Something thats been in development for even 5 years and doesn't show any concrete signs of success should at least have alternatives developed for it. After 5 years if you still can't say for certain if its ever going to work, you definitely need to start looking in different directions.
Why does Intel need to push the envelope that hard and that fast just to create a product that will, in the end, have extremely low yield and extremely high cost?
Just so they can adhere to some ancient "law" proposed by one of their founders? It's time to let go of Moore's Law. It's outdated and doesn't scale well... just like the x86 architecture! *ba-dum, chhh*
I think there has been a major article asking this question every six months for the last decade. Then: surprise surprise, there's a new tech development that improves the technology. We've been "almost at the physical limit" for transistor size since the birth of the computer, why will it be any different this time?
Well I can say with absolute certainty that they will not go below the Planck length.
'We are trying to prove ourselves wrong as quickly as possible, because only in that way can we find progress.' RPF
The latest revision of my Phenom II X4 disagrees with you. The Phenom II series is absolutely steamrolling over every other Intel product in its price range.
Hint: Notice I said "in its price range." Because not everyone prefers spending $1300 on a CPU that's marginally better than one at $600. It seems like Intel has stepped away from the "chip speed" game and stepped right into "ludicrously expensive".
The only Intel chips that are $1000+ are those that are either a few months old and/or are of the "Extreme" series. The core i7-860s and 930s are under 300 bucks and pretty much the entire core i5 line is at 200 or less.
You have an uncanny ability to predict the present!
Larger dies generally cost more because it's more likely that they'll have a defect. I haven't done any chip design since college (and even then it was really entry level stuff) but if you could break the chip down into 10 different subcomponents that need to be spaced out, you could put 100 of those components on the chip and then after manufacture you could select the blocks that perform best and are defect free, spacing your choices accordingly.
I'm pretty sure chip makers likely already
It has always been about making it smaller. Clock speed was able to increase because the chips got smaller. We were able to add more cores per die because the chips got smaller. Moore's law is about size: it doesn't say computers will get faster, it says they will get smaller.
What we are able to do with the smaller chips is what's changed. Raising the clock speed worked for years, and that is the best option, but because of physical problems, in the latest generations we weren't able to do that. So the next best thing is to add cores. Now the article is suggesting we may not even be able to do that anymore.
I will tell you I've been reading articles like this for as long as I've known what a computer was, so if you're a betting man, you would do well to bet against this type of article every time you read it. But in theory it has to end somewhere, unless we learn how to make subatomic particles, which presumably is outside the reach of the research budget at Intel.
Qxe4
The article mentions "dark transistors", which are transistors on the chip that can't be powered because you can't get enough power onto the chip. This is the problem that reversible computing was supposed to solve.
Since they are so parallel they are made as a bunch of blocks. A modern GPU might be, say, 16 blocks each with a certain number of shaders, ROPs, TMUs, and so on. When they are ready, they get tested. If a unit fails, it can be burned off the chip or disabled in firmware, and the unit can be sold as a lesser card. So the top card has all 16 blocks, the step down has 15 or 14 or something. Helps deal with cases were there's a defect, but overall the thing works.
What are you talking about? AM2 boards support AM3 chips.
You also present a false dichotomy, because upgrading isnt ONLY about buying suboptimal hardware and then upgrading it later. Anyone who purchased bleeding edge AM2 gear when it was introduced can get a bios update and then socket an AM3 Phenom II chip. They still only have DDR2, but amazingly Phenom II's support both DDR2 on AM2 and DDR3 on AM3.
So that guy who purchased a dual-core AM2 Phenom when they were cutting edge can now socket a hexa-core AM3 Phenom II.
Its amazing what designing for the future gives your customers. Intel users have only rarely had the chance to substantially upgrade CPU's.
"His name was James Damore."
Well done, you've just described... today!
And today, we already know the problem with this approach: most everyday problems aren't easily parallelizable. Yes, there are specific areas where the problems are sometimes embarrassingly parallel (some scientific/number crunching applications, graphics rendering, etc), but generally speaking, your average software problem is unfortunately very serial. As such, those multiple cores don't provide much benefit for any single task. So if you want to execute one of these problems faster, the only thing you can do is ramp up the clock rate.
For one, Itanium is still going strong in high end servers. It is a tiny market, but Itanium sells well (no I don't know why).
However in terms of the desktop, you might notice something: When AMD came out with an x64 chip and everyone, most importantly Microsoft, decided they liked it and started developing for it, Intel had one out in a hurry. This doesn't just happen. You don't design a chip in a couple months, it takes a long, long time. What this means is Intel had been hedging their bets. They developed an x64 chip (they have a license for anything AMD makes for x86 just as AMD has a license for anything they make) should things go that way. They did and Intel ran with it.
Ran with it well, I might add, since now the top performing x64 chips are all Intel.
They aren't a stupid company, and if you think they are I'd question your judgment.
People have been proposing circuits for regenerative switching (mainly for clocking) for a long long time. The problem always being that if you add an inductance to your circuit to store and feedback the energy, you will significantly decrease how fast you can switch.
Also, you think transistors are difficult to build in small sizes? Try building tiny inductors.
Actually, it's pretty common practice to put spare arrays and spare cells in the design that aren't connected in the metal layers. When a chip is found defective, the upper metal layers can be cut and fused to form new connections and use the spare cells/arrays instead of the ones that failed by use of a focused ion beam.
But that still adds time and cost. Decreasing die area is pretty much always preferable. Also, larger dies means even more of the chip's metal interconnects have to be devoted to power distribution.
I'd settle for less bloat-ware. Back in the day amazing things were done with extremely limited CPU resources by programming closer to the wire. Now we have orders of magnitude more resources but most programming is done at a very high level with numerous layers of inefficiency which negates, possibly more than negates, the benefits of increased CPU resources. Yes, yes- I wax a little "in my day/up hill both ways, etc." but do the benefits of high level programming and efficient use of resources have to be mutually exclusive?
How about writing better software. Stuff that doesn't require 24 cores and 64GB of RAM?
Because X-rays are .01 - 10 nm light and EUV is 13.5nm light... so nothing to do with the word, as much as engineers like to label things correctly.
graphene.
(can't go faster, so lets just go the same speed, but in parallel).
Actually they do go faster. Clock speed doesn't mean processing speed. Modern CPUs do much more per clock cycle than their predecessors because of their greater instruction-level parallelism, shorter instruction latencies, larger caches, etc. While their cores don't generally operate at a higher frequency, they perform many times faster.
That's not even considering the additional cores and massively improved power efficiency. It's difficult to overstate just how fucking amazingly good CPUs are now.
Trust me, what you're seeing is *not* what you think you're seeing. Windows isn't magically auto-parallelizing your code. That's a hot topic of research today, and it's really fucking hard.
because "X-rays" is such an UGLY word....
There's actually some truth to this. Originally it was called soft x-ray projection lithography. The other type of x-ray lithography was a near contact shadow technique using shorter (near 1nm) x-rays. To distinguish the two techniques they changed the name from soft x-ray to EUV.
This was also done for marketing reasons. X-ray lithography had failed (after sinking a lot of $$ into it), while optical lithography had successful moved from visible to UV, to DUV. By calling it EUV it sounds like the next logical step, instead of being associated with the failure that was x-ray lithography.
(Actually, x-ray lithography didn't really truly fail. It does work, but optical surpassed it before it was ready, so it became pointless)
Actually, 3D has picked up quite a bit in the last few years. However, the primary interest is connect different chips together in the same package with short, fast, interconnect. It's a lot better than conventional System In Package and much much better than circuit board connections. Unfortunately, the connections are a bit too coarse to spread a single design like an Intel processor across the layers.
For that you need more sophisticated methods like growing a new wafer on top of one that has already been built up. These methods are not yet ready for production.
another problem is that adding cores is not as effective, right now, as upping clock speed.
this may change however if the designs change from multiple universal cores to something more like a the cell cpu that powers the playstation 3, or maybe something like the the latest GPUs. Basically, a couple of universal cores like before (as they provide some benefit, if the os do a proper job in spreading processes across them) combined with multiple simpler cores that can be arranged like a assembly line. Then you stuff data in at one end, have each core do it assigned task in the chain, and have the result come out the other. With enough of them, one start to approach something like FPGA, giving each logical instruction in a program its own core.
This is interesting in that a recent presentation i found the video of, stated that cpus these days slowed down mostly because it needed something from cache (usually because of a bad speculation during a IF or similar divergent routes in the code).
comment first, facts later. http://chem.tufts.edu/AnswersInScience/RelativityofWrong.htm
This review:
http://it-review.net/article/hardware/cpu/Intel_Core_i7_980X,_Core_i5_650_and_Core_i3_530_review&3
These processors:
Core i7-980X
http://www.newegg.com/Product/Product.aspx?Item=N82E16819115223
Core i5-650
http://www.newegg.com/Product/Product.aspx?Item=N82E16819115220
Core i3-530
http://www.newegg.com/Product/Product.aspx?Item=N82E16819115222
Notice the performance of the 980X over the other two. There's no more than a 3x performance increase in media encoding. Compare the price tag differences, ranging from a six-fold increase over the i5 and an eight-fold increase over the i3.
The kind of premium Intel charges for the "Extreme Edition" brand is ridiculous. Based on those specs alone and knowing the price of the two lower models, I wouldn't expect to be charged anything more than $600 for the i7.
You asked me to provide evidence supporting my claim of 2x performance gains and 8x the pricetag. I did exactly that. AMD and Intel may be in a tight race at the midrange ($140-$200) but the interoperability between AMD's three socket specs (AM2,AM2+,AM3) and the DDR2/DDR3 backwards compatability are what send AMD leaps and bounds ahead of Intel. From a holistic standpoint AMD's offering is alot more stable in the long-term, and this is how they steamroll over the competition.
P.S. I got fed up with Intel when I found out I'd have to throw out my motherboard, CPU and RAM to move from a Core2 Quad to *any* of the i3/5/7 offerings. My motherboard, CPU and RAM were no more than two years old and yet somehow there was no financially sane upgrade path for ANY of the components. If I were to get an i3 or i5, that meant I most likely couldn't upgrade to an i7 later without chucking the entire motherboard. This is what ticks me off about Intel's business model.
Folks don't often realize how much work we software writers go through to write this big, complex, core-eating software. Back in the day with 8-bit 500 KHz CPUs we could write a simple 1000-iteration loop with a bit of code in it, and it might lag the CPU for a whole second. Now with these fast processors we have to go through all kinds of hoops to use up all those cycles! Building languages on top of languages, interpreted languages, all kinds of extra error checking (error checking can often take 80%-90% of the cycles and code), objects on top of arrays on top of pointers on top of objects ... you get the idea. SOMEBODY has to make the software to use up all those cycles.
It's a dirty job, but somebody has to do it!!!
WE CAN NOT LET THE HARDWARE PEOPLE WIN!!! For every added processor, every bump in Hz, we WILL come up with a way to burn it! Soon we will embark on the new 3D ray-traced desktop - THAT will keep the HW folks busy for a while!!! And (don't tell anybody) soon we will establish the need for full time up-to-date indexing of everything on the LAN. Of course, that could be done by one machine, but if we all do it independently on each machine, that will burn another whole 2GHz CPU's worth of cycles.
Our goal and our motto: "A computer is nothing but a very complicated and expensive heater." :D
It's easier to be a result of the past, but more fun to be a cause of the future! http://www.spacefinancegroup.com/
Another critical dimension is gate thickness. When you speak of a 16 nm process, you are (generally) talking about the minimum dimension in the XY plane, which is usually reserved for gate length. Gate thickness is a much smaller dimension, and if I recall correctly we're already down to about 4 molecules of thickness. Quantum tunneling is a problem.
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