Intel Unveils Next Gen Itanium Processor

MojoKid writes "This week, at ISSCC Intel unveiled its next-generation Itanium processor, codenamed Poulson. This new design is easily the most significant update to Itanium Intel has ever built and could upset the current balance of power at the highest-end of the server / mainframe market. It may also be the Itanium that fully redeems the brand name and sheds the last vestiges of negativity that have dogged the chip since it launched ten years ago. Poulson incorporates a number of advances in its record-breaking 3.1 Billion transistors. It's socket-compatible with the older Tukwila processors and offers up to eight cores and 54MB of on-die memory."

Comments

His name was Robert Paulson

[GoNINzo]

Guess the guys at Intel have been watching Fight Club a little too much.

Re:His name was Robert Paulson

[fuzzyfuzzyfungus]

"I understand. In death, we have names..."

This the itanium team; but could they have chosen something a little less, er, pessimistic?

Re:His name was Robert Paulson

[magamiako1]

I came here just for this, and you delivered. Bravo.

Re:His name was Robert Paulson

[Anonymous Coward]

"His name was Robert Paulson." This is precisely what I was thinking. Kudos for reading my mind.

Re:His name was Robert Paulson

[Anonymous Coward]

Nah I think it was Henry Paulson, ex-CEO Goldman Sachs, Bush's Treasury Secretary who instigated the TARP bailout.

A rather hip reference to the house of cards Wall Street built atop subprime mortgages, calculating credit-adjusted values using Intel's original Pentium FPU....

Re:His name was Robert Paulson

[muckracer]

> This the itanium team; but could they have chosen something a little less, er, pessimistic?

Well, this IS Project Mayhem...! :-)

Re:His name was Robert Paulson

[RyuuzakiTetsuya]

I think IBM's POWER team and AMD better check their basement for strange looking white trucks...

Poulson

[Anonymous Coward]

Its name is Robert Poulson

Itanium flashbacks

[ArhcAngel]

Does anyone else cringe when they here Itanium? The early chips still give me nightmares.

Re:Itanium flashbacks

[FooAtWFU]

Obviously, lots of people cringe, and even TFS refers to it as a possible redemption of the Itanium line's name (i.e. its reputation was pretty lousy to begin with).

Re:Itanium flashbacks

[Anonymous Coward]

may also be the Itanium that fully redeems the brand name

Conversely, it may NOT.

Re:Itanium flashbacks

[Anonymous Coward]

I work with the world's foremost experts on optimizing for Itanium 2. All available compilers suck. If you are willing to invest the effort to hand tweek, you can squeeze amazing performance out of the processors. They are extremely memory bound (hence 54MB cache now on chip). It is usually faster to recalculate numerical values than to fetch stored results.

We work with large high performance computing systems/clusters. IBM Power 7 is fastest hands down for numerical work if you plan to use the crap output from the compiler directly. Recent Intel Xeon is as fast as Power 7 if you adjust all the fiddly settings and use some trial and error, but Xeon doesn't scale well for Symmetric Multi-Processing (SMP). Itanium 2 wins by a bit if you invest huge effort. Power 7 would probably be fastest overall for numerical work if we invested the same effort into optimizing that we do for Itanium. However, we don't have to invest the effort for Power 7 to be "fast enough".

Re:Itanium flashbacks

[Anonymous Coward]

The graph in TFA showing sales projections versus year is hilarious. The actual sales line barely registers on the scale of the initial projections.

Re:Itanium flashbacks

[Anonymous Coward]

I cringe when people write "here" when they mean "hear."

Or "it's" when they mean "its"

And to, too, and two. etc

Yup, sometimes my fingers type here when I meant hear, etc. That's why I read what I wrote before I press Submit.

Re:Itanium flashbacks

[Anonymous Coward]

I twond that.

Re:Itanium flashbacks

[TheLink]

Would the same optimizations for the Itanium work OK for the Itanium 2 and for the upcoming Itanium? Or would the optimizations be too generation specific?

AFAIK the problem with the Itanic was the Itanic was better at "embarrassingly parallel" problems. But that meant you could usually get the same (or better) performance with two or more x86 servers at a lower cost... And the x86 processors would do better than the Itanic on code that's not been optimized by super experts.

Re:Itanium flashbacks

[Anonymous Coward]

The big problem is that the new chip has doubled the issue width. For the Itanium 2 you would write code to execute 6 instructions in parallel; now you want to run 12 instructions in parallel. The optimization is still the same in principle (you're just tweaking a parameter from 6 to 12 for code generation) but even getting 6 instructions together without a stop was very difficult in some situations. Architecturally it's all still the same, though.

Re:Itanium flashbacks

[mevets]

| I work with the world's foremost experts on optimizing for Itanium 2....

So when your whole team orders lunch, do you get a medium pizza or a large?

Re:Itanium flashbacks

[the linux geek]

It looks like it's just going to execute two threads in parallel, with an instruction bundle from each thread every cycle. That shouldn't be too bad, as long as you have two CPU-bound threads... this almost looks like it's comparable to a 16-core "Tukwila."

Re:Itanium flashbacks

[Nikker]

You might be under estimating the size of our employee.

Re:Itanium flashbacks

[LWATCDR]

Memory bandwidth seems to be the next big bottle neck. I wonder what is the "ideal" memory to CPU ratio.
I wonder what it would be like to have a system with no real ram just cache. Imagine CPUs with 4 GB of cache in a system where all the memory above 32bits was the cache of another CPU. You could access the memory of the other CPU as the speed of RAM today. It would be a really massive MP system to be sure. Of course then you would still want some RAM even if it just for DMA IO and Video.
Yea I am sure I am combing up with a total fail at some level and some EE on here will tell me why but from a software point of view it interests me.

Re:Itanium flashbacks

[Anonymous Coward]

Bullshit. Names and places or it didn't happen.

Says AC.

(Says AC.)

Re:Itanium flashbacks

[gsgriffin]

I work for the world's secondmost experts on optimizing for Itanium 2. We order a small pizza. Usually we're not that hungry after a half-days work on this. We've lost our appetites completely by the end of each day.

Re:Itanium flashbacks

[Paracelcus]

I was a contractor when they were working on this "next gen" 64bit CPU everybody was excited, then later when I read about it, I couldn't understand where this new architecture would fit. Then X86/64 came out and there really seemed to be no place for it.

IMHO, don't throw good money after bad.

Re:Itanium flashbacks

[Mr Z]

The cache has to be backed by *something*. Either that, or you have to have some protocol wherein when you kick the last copy of something out of one cache, you arrange for it to get stored in another, in which case it isn't really a cache at that level so much as a set of dynamically assigned addresses system-wide.

Consider a smaller system first as an example. Suppose you had two CPUs, each only one level of cache, and each with 1MB. That's 2MB total system memory. Now suppose the first CPU reads through all 2MB twice, bringing all of it through its 1MB cache. It'd have to send the bits it wasn't using to the other CPU's cache while it wasn't stored in its own cache--ie. it's have to exchange data with the other cache as opposed to merely copying it as caches do today. The net effect is that you're just changing the current home for the data, since there's no system RAM outside of these "caches" that serves as the canonical home for the data .

It's not that such a system couldn't work, but it would probably be impractical for large memories and certain workloads. For example, suppose both processors are reading from the same large database, and the database is largely read-only. In this system, there's no opportunity for both CPUs to simultaneously have a copy of the data that they're both sharing. The data would have to ping back and forth

You could combine this with more ordinary caches. For example, add another 512K cache to each CPU between the CPU and the 1MB I described above. Now the CPUs could each have copies of read-only stuff and shared stuff, but the final home for the data would still migrate among the CPUs. It'd perform OK until you stopped fitting in the smaller cache. This is roughly what large NUMA machines do with page migration. The operating system has to manage that though to make it work well. Normal virtual memory translation mechanisms allow you to move a virtual page to different physical memories attached to other CPUs without the application knowing. It's like the cache idea you described, but managed by the OS.

The problem with huge hardware caches is the lookup penalty. For each cache block, you have to keep track of what address maps to the cache block. If you're distributing this through the system, then you need some sort of directory mechanism to find the cache block of interest. This isn't intractable mind you--it's a similar problem to finding a cell phone in the cell phone network, but it is expensive and complicated to get right in hardware. And unlike the cell phone network, it can't just send a call to voice mail when it can't find what it's looking for. That's why we push much of this to software and let the OS handle it at the page level. It can apply more sophisticated algorithms, and crucially, it can be patched when we find bugs.

Re:Itanium flashbacks

[Chris Mattern]

Personal pan pizza, I'm betting.

Re:Itanium flashbacks

[Chris Mattern]

So it runs like a bat out of hell when you massage it correctly. Good for you. Know what we call a processor that nobody can write a decent software stack for? A shitty processor.

Re:Itanium flashbacks

[LWATCDR]

I was thinking of Cache as being more like on board fast ram that ran at CPU speed than as cache as we see it today.
To take your database example the way I imagine it working is a CPU would send commands to all the CPUs to find the records that contain x. Each CPU would search it's own memory of records and then just transmit the records to the requesting CPU. It would take a differn't programing model that what we use today. In a way I was thinking of it as smart ram. It seems dumb that a CPU has to read a value do a compair and then read the next value. If the CPU could send a command to the ram to incement a value or do search it contents for a string or values you could really cut down on the memory band width.
But this is all pipe dreams from a software guy so any hardware experts just understand that I am just thinking out loud and really do not think I know more than you guys do.

Re:Itanium flashbacks

[TheRaven64]

I work with the world's foremost experts on optimizing for Itanium 2. All available compilers suck.

I sometimes work on compilers for HPC, and this is caused by two, related, things. The first one is that no one cares. Itanium is such a small market that, even if you can get both Itanium users to buy your compiler, it's not worth the investment.

IBM Power 7 is fastest hands down for numerical work if you plan to use the crap output from the compiler directly.

POWER 7 is a pretty generic RISC design with a few CISCy tweaks. We've got 40 years and millions of dollars of research to look at when designing compilers for it. For Itanium? Not so much. It doesn't help that Itanium is so unlike everything else that it's hard to share optimisations. Optimisation code in the middle end can be shared easily among MIPS, SPARC, and POWER, and mostly with x86, but with Itanium may actually be pessimising the code.

It's a shame, because I actually like a lot of things about the Itanium, and I'd be quite interested in working on optimisations for it, but no one is willing to pay enough to make it worthwhile.

However, we don't have to invest the effort for Power 7 to be "fast enough".

POWER has the same advantage that C has, when it comes to performance: a pretty crappy compiler can give good performance. Take a look at TCC sometime - it's about as primitive as it's possible to be and still be a C compiler, yet still delivers okay (though not great) performance in most cases. Now compare a crappy Java implementation to a good one - the difference is far more pronounced. It's the same with Itanium - the compiler needs to be very clever to get good performance, and for the same reason. C presents the programmer with an abstract machine that is basically a PDP-11, and the POWER 7 is sufficiently similar to a PDP-11 that it's a pretty trivial mapping. Once you've done that, you can tweak for more performance. Java presents an abstract model closer to a B5000, so you first have to map that to something more like a PDP-11, then to the native chip. The Itanium provides a concrete model that is not very like the C abstract model, so compiling C for Itanium is a pain. Something like APL might be easier, but I've not heard of anyone actually using APL for a while.

Re:Itanium flashbacks

[Anonymous Coward]

From a software perspective, all you are asking is: what would a ccNUMA machine look like if the local memory on each node was as fast, small, and expensive as today's level 2 (or level 3) cache? You would also still need local buffer/cache for handling the remote memory contents while you are in the process of reading or writing them, but that's just a minor detail.

Re:Itanium flashbacks

[MiniMike]

They order 8 personal pizzas, all to be put in the same box. Only one person at a time is allowed to remove a slice.

Re:Itanium flashbacks

[Simon80]

I'm not a hardware guy, but what you're saying is out of touch with the design tradeoffs CPU designers already make for the following reason. Memory that runs at CPU speed already exists, that's what registers are. Then you have L1 cache, which takes a few cycles to access, L2, which takes I don't remember, a few dozen cycles, and memory, which takes hundreds of cycles, even longer if the TLB cache is being missed as well. Obviously things go faster if you have more registers, more L1, etc., but it's a tradeoff between cost, opportunity costs, and performance. Even if you had copious amounts of these on-die caches, you'd still want more RAM, so that you'd have something to put into the caches instead of limiting the working set size to the size of the cache! Furthermore, there is a hierarchy of storage that looks something like registers > L1 > L2 > L3 > memory > SSDs > disk storage > LAN > WAN. Of course, disk storage would be behind information stored in memory of another CPU node in a supercomputer, but anyway, the point is that the faster tiers are there to make access to the slower ones seem faster than it would be if the slow tiers were accessed directly. If you want to be able to write fast software, I suggest you read Ulrich Drepper's What Every Programmer Should Know About Memory. It's not that long, and very informative.

Re:Itanium flashbacks

[LWATCDR]

I do understand that is why I said I wonder what the ideal trade off between memory and CPU will be. Right now such a system would be useless because caches are only a few MBs. What happens when we can put 4 GB on the die? There are very few problems that can not fit in 4GB. I do understand the register, L1, L2, L3, main memory, mass storage structure. But we are already having memory access issues and moving to more and more cores. There is just a really nice symmetry to each CPU having 32 bits of CPU speed memory and then using the upper 32 bits to address the local memory of other CPUs. Sort of like how the Connection Machine used masses of dumb CPUs this would use masses of a lot more powerful CPUs. Sure it would not be for a desktop but for massive parallel programs where each problem unit can fit in a 32 bit address space.
And you are right that this like the connection machine isn't the ideal solution.

Re:Itanium flashbacks

[bromoseltzer]

...If you want to be able to write fast software, I suggest you read Ulrich Drepper's What Every Programmer Should Know About Memory. It's not that long, and very informative.

It's 114 pages of not that long, but who's counting?

Re:Itanium flashbacks

[Simon80]

..and what happens to your performance if you don't distinguish remote memory from local memory? Also, there are tons of problems that don't fit into 4GB, such as, for example, pretty much every problem that involves using a database. Even so, at some point cache limitations cease to be the bottleneck. Keep in mind that all of that die space can be used to implement more cores, etc., so it's not as simple as "how much cache can we fit on the die", there's always a tradeoff between competing uses for the die space, and more importantly, for your money.

Re:Itanium flashbacks

[Simon80]

Well, if you're not serious, then yes, it's long, but if you have a serious specialization in software development then it's a drop in the bucket. Anyway, it's short compared to reading a book, and he's nice enough to not even make you pay for it.

Re:Itanium flashbacks

[turgid]

I knew a guy who had one once. He used to use it for drying his clothes.

The marketing hype made me cringe. It was pretty obvious that the whole thing would be a disaster from the start.

itanic relied on "good compilers" to get any performance. However, compilers that "good" will never be made, since you can't write a compiler that can predict the future.

However, you can put hardware in your CPU to reorder instructions at run time based on observations of the behaviour of the running code, speculatively execute certain code paths, predict branches and swap to a different thread context when the current one stalls waiting for memory to catch up...

Re:Itanium flashbacks

[Rockoon]

The size of on-chip cache determines its latency. Larger caches are slower because they HAVE to be, not because they are made of different stuff.
The first-order reasons is distance. The L1 is closest to where the data is needed, the L2 farther away, and the L3 still farther. Its not possible to simply make the L1 larger without also increasing the largest distance and thus its latency.
So the L1 is kept small on purpose, to reduce its latency (to 2 or 3 clock cycles these days)
Trust me. The CPU manufacturers arent stupid. Their cache size choices are pretty close to optimal given the workloads they expect of their processors.

Re:Itanium flashbacks

[Anonymous Coward]

If you are willing to invest the effort to hand tweek, you can squeeze amazing performance out of the processors. They are extremely memory bound (hence 54MB cache now on chip). It is usually faster to recalculate numerical values than to fetch stored results.

You realize that you've just described every modern general-purpose processor, other than the details of the cache size?

Re:Itanium flashbacks

[David Greene]

What happens when we can put 4 GB on the die?\

You will have a very slow cache.

Re:Itanium flashbacks

[Fulcrum of Evil]

Have you played around with Opterons? I'd like to hear if they stack up any differently to the Xeons.

Re:Itanium flashbacks

[linest]

Here, here!

Re:Itanium flashbacks

[petermgreen]

AIUI while itanium was a failure on the desktop and windows/linux server intel was successful in pulling a number of vendors (HP being the best known in the west) into using it for their unix and/or mainframe systems and sales for that purpose provide Intel with enough revenue to justify keeping it alive.

Re:Itanium flashbacks

[bill_mcgonigle]

I sometimes work on compilers for HPC, and this is caused by two, related, things. The first one is that no one cares. Itanium is such a small market that, even if you can get both Itanium users to buy your compiler, it's not worth the investment.

I heard a story from a guy at Redhat that the team that maintains the Itanium port was putting together a pool to buy the last remaining Itaniums from the customers (for more than it would cost to replace them) and then throwing the Itaniums off the roof.

Re:Itanium flashbacks

[Anonymous Coward]

I All available compilers suck. If you are willing to invest the effort to hand tweek, you can squeeze amazing performance out of the processors.

In other words, you have never touched an itanium. LOL. Kids posing like that these days.

Re:Itanium flashbacks

[Anonymous Coward]

I work with the world's foremost experts on optimizing for Itanium 2. All available compilers suck.

On behalf of the compiler developers of the word: It's not our fault. IA-64 is very, very hard to generate good code for, and there's the added Catch-22 that nobody is willing to pay for the considerable research effort required because not enough people use it.

Intel knew that IA-64 was going to require new compilation techniques when they designed the ISA. They took a gamble that those techniques would be available soon enough. They lost that bet.

Re:Itanium flashbacks

[TheLink]

Doesn't that mean they'd have to recompile to get any speed ups (other than clock speed increases)?

Whereas with the x86, old code could in many cases still run faster due to the processor doing the parallelization internally.

Re:Itanium flashbacks

[sjames]

I'm pretty sure he meant that what is now cache on the CPU would be configured as RAM but still as fast (or faster) than the current cache.

Re:Itanium flashbacks

[Mr Z]

He used the phrase "No real RAM, just cache." I work with embedded processors that split their memories between cache and RAM (many of the C6000-family DSP cores), and also work with processors that are all cache (most general purpose processors). The phrase "no real RAM, just cache" implies that there wouldn't be any directly mapped memory, only indirectly mapped memory (ie. "cache" by his definition).

How else would you interpret "no real RAM, just cache"?

Re:Itanium flashbacks

[sjames]

Some people interpret "Real RAM" to be dimms stuck in sockets and cache to be stuff on the die with the CPU (not me personally, but it's not the first time I've heard it). Agreed it's not technically correct, but there it is anyway. In any event, that's the interpretation that makes the proposal sensible..

At least in Coreboot, the boot CPU's cache is used as RAM until the actual RAM can be initialized. It works as long as nothing is done to trigger a writeback.

Re:Itanium flashbacks

[Anonymous Coward]

No, not really. It's up to the programmer/compiler to put a "stop" at the end of a bundle if it can't be done in parallel with the next bundle. Currently if you have 4 bundles, there's no reason to put a stop after the 2nd one, even if only 2 bundles would be issued concurrently.

Huhh, what's next rebirth of MIPS?

[Anonymous Coward]

I didn't know that Intel still made Itanium's! Have to wonder if the old SGI MIPS chips will end up staging a comeback!

Re:Huhh, what's next rebirth of MIPS?

[armanox]

Oh, but MIPS are still being used commonly. http://www.mips.com/

Re:Huhh, what's next rebirth of MIPS?

[TheRaven64]

SGI isn't making MIPS chips, but a lot of other companies are. As I said in another post, I sometimes work with a company that produces compilers for HPC, and they are seeing a lot more demand for MIPS than for Itanium. A lot of interesting processors are using the MIPS instruction set. It's cheap to license, so companies wanting to do things like put 64 cores on a chip just license MIPS. There's also the Chinese version, which is starting to look quite respectable - especially in price/performance metrics.

Re:Huhh, what's next rebirth of MIPS?

[AaronW]

The company I work for makes 64-bit MIPS processors with up to 16 cores (soon 32 cores). They're optimized for I/O, networking, storage and security and lack floating point though. The nice thing with MIPS is that it's easy to extend the instruction set without breaking anything. We've added a number of instructions and have extended gcc/binutils to take advantage of it. And yes, they all run Linux.

Being a traditional RISC type platform makes it not too difficult for the compiler to optimize code for.

Re:Huhh, what's next rebirth of MIPS?

[TheRaven64]

We've added a number of instructions and have extended gcc/binutils to take advantage of it.

And this is the bit that makes so many people hate MIPS. Every vendor has their own GCC / binutils fork, often based on an old version, with patches that can't be pushed upstream without breaking other architectures.

Re:Huhh, what's next rebirth of MIPS?

[AaronW]

Actually ours is in the mainline gcc, so there's no special fork unless you want the bleeding edge support, which always takes a little while to get checked in to the main branch.

Re:Huhh, what's next rebirth of MIPS?

[dido]

The MIPS architecture is alive and well from the looks of things, and not just in the realm of HPC, and it is probably the most popular RISC CPU architecture in history. I carry such a processor around with me every day in the form of a CXD2962GG CPU in my Sony PlayStation Portable, which is essentially a clone of the MIPS R4000. The PSX used a MIPS R3000-family CPU that was essentially the same as what you would find inside an old SGI Indigo. Apparently the PS2's Emotion Engine was actually a MIPS III/IV architecture CPU with extra SIMD instructions similar to Intel's MMX/SSE. I imagine that MIPS-architecture processors are even more common in embedded systems.

Whytanium?

[Anonymous Coward]

Seeing as how Itanium has already failed at its core objective, why is Intel continuing to push it?
Is it just a guilty conscience over coercing HP into dumping Alpha?

Re:Whytanium?

[NewWorldDan]

I was a little surpirsed to learn it was still being produced. I thought it had quietly been discontinued. I don't personally know anyone who operates an Itanium based server.

Re:Whytanium?

[pantherace]

It's the only place people can get VMS, or HP's UNIX.

Which is a shame, because VMS has some interesting and nice features, so even if it weren't used wholesale, more exposure could lead to other OSes implementing them.

Re:Whytanium?

[Erich]

Are there more people on Itanium VMS than Alpha yet? I hadn't heard that was the case...

Re:Whytanium?

[gstoddart]

It's the only place people can get VMS, or HP's UNIX.

Wow ... I'm shocked that VMS still exists. I haven't heard anybody mention that in a long time.

Which is a shame, because VMS has some interesting and nice features

Like what? It's been so long since I've seen it, I've long since forgotten almost everything about it. I'm surprised there's cool OS features that everyone else hasn't stolen -- that is, of course, assuming they're actually useful for anybody.

Re:Whytanium?

[the linux geek]

Itanium is the #2 high-end UNIX server processor, ahead of SPARC but behind POWER. Itanium systems get between $4bn and $5bn and sales, and are growing. It didn't meet the original goal of taking over the world, but I don't know what parallel universe you live in to think it's a failure.

Re:Whytanium?

[Anonymous Coward]

Believe it or not, the rate of sales for Itanium chips increases every year. It just increases very very very very slowly. $5 billion/year in revenue may be peanuts for Intel, but it's still better than $0 billion. Itanium's Intel's best chance to compete head-on with POWER, though it's been losing pretty handily :P

Re:Whytanium?

[Muad'Dave]

Automatic versioning of files, for one thing. That was kinda neat - you could tell the filesystem to keep 'n' versions and could access them explicitly like hello.c;3. The OS would return the last revision if you didn't specify the version.

Re:Whytanium?

[Anonymous Coward]

I'm sure this and
this are clear signs that everything is A-OK with everyone being cheerful and optimistic about the future of the platform.

Re:Whytanium?

[Anonymous Coward]

UNIX? You mean that quirky little time-sharing system for minicomputers?

Re:Whytanium?

[the linux geek]

The fact that there was any meaningful Linux/Windows support was a vestige of the time when Intel saw a future where Itanium would replace commodity processors at the low end. Neither SPARC nor POWER has Windows support, and SPARC doesn't have any Linux support from a major distribution either. This is because Nobody Cares about Linux for enterprise platforms, except for consolidating x86 workloads... and IBM is the only company aggressively going after that market anyway. The vast majority of high-end enterprise servers run UNIX or proprietary operating systems.

Just because you run Linux in your basement doesn't mean it dominates high-end servers.

Re:Whytanium?

[gstoddart]

Automatic versioning of files, for one thing

Ah, yes. I had forgotten that one ... that came in handy when I was in university.

Re:Whytanium?

[pleappleappleap]

I'd doubt there are more people on Itanium VMS than on VAX. LOL

Re:Whytanium?

[operagost]

Like what?

Real ACLs? Real clusters, even over TCP/IP WANs? RMS? Not crashing? A filesystem that doesn't corrupt your data, even if you do crash?

Re:Whytanium?

[Anonymous Coward]

the military's legacy healthcare system CHCS is transitioning from Alpha to Itanium. I quit that gig but it would have been nice to see the old washing machines go away (Compac GS140's)

Re:Whytanium?

[ebh]

Ahh, the least-used feature of the CD-ROM file system, (ISO-9660), specifically included for backing up VMS file systems.

Re:Whytanium?

[SharpNose]

{ shocked }Looks up from his Sun Sunfire V240 w/ UltraSPARC that runs fully modern Gentoo Linux perfectly well...{ /shocked }

Re:Whytanium?

[the linux geek]

"Major distribution," in this case, meant commercial support - since the parent had been complaining about lack of RHEL.

Re:Whytanium?

[default luser]

Itanium is the #2 high-end UNIX server processor, ahead of SPARC but behind POWER. Itanium systems get between $4bn and $5bn and sales, and are growing. It didn't meet the original goal of taking over the world, but I don't know what parallel universe you live in to think it's a failure.

It is a failure simply because the cost of engineering a new processor architecture is not really recouped by the current sales. Let's take a look at the math:

1. It costs hundreds of millions of dollars to design a new CPU architecture. A basic CPU design can cost over 100 million dollars (4 years, 100 men). Let's guesstimate somewhere closer to $150-200 million for a new Itanium release, since this is a high-end multiprocessing chip that's on-track to take 5 years to develop

So, they design their new CPU...now they have 2.5 years to make money off the architecture before it gets replaced. So, how much money do thy really make on Itanium?

2. HP's System Sales were 4.4 Billion in 2008 (3.5 Billion in 2009, I noticed you chose to ignore that), but Intel only gets a tiny chunk of that total system cost, because they only make the processor and chipset.

Take Tukwila, for instance: the top price per-processor (9350) is nearly $4000, but you can bet the most sales are in the realm of the $2000 (9330, 9340). Let's split the difference and overestimate the average selling price per-socket at $3000 (this would also include the chipset).

According to industry analysts, Intel makes about 200,000 Itanium processors in a year (2007). After the sales hit in 2009, I'm inclined to think this is still accurate. 200,000 x $3,000 = $600 Million in revenues, which is a Intel's cut of the total system sales.

Now, consider manufacturing costs to Intel (not included in the architectural development). Tukwila is a huge die size (very few CPUs per-wafer, much room for defects), and the processor is advertised as having top-end RAS in the sales pitch, so you can bet they test and discard many cores that would have passed normal desktop CPU tests. The cost of wafers, testing and defect throwaways will be a huge percentage of the cost of the chip - I'd say at least %30, and could go as high as %50. So take that off the top of 600 million, and you're left with 300-400 million. Add in the costs of advertising, maintaining (and improving) the development toolset of your proprietary architecture (who else is going to do it?), and real profits for a year could be as low as 200 million.

So, over the course of a 2.5-year product cycle, Itanium earns Intel somewhere between 500 million to 1 billion dollars in real income, minus the $150-200 million to develop. That's a pretty sorry amount for a company that makes almost 12 billion net per-year.

Intel would be better served spending this money on their top-end Xeon processors. Right now, Itanium is NOT a real growth market - the recent spikes were because of people fleeing PA-RISC and Alpha, and those sales will die-off. The only real growth potential for Intel would be to add the same level of RAS to their top Xeon line, and entice people away from RISC with the incredible support and toolset of x86-64.

Re:Whytanium?

[bored]

Yah, and probably over half of the actual applications are running in PA and Alpha translations mode on HP-UX or VMS. The IA market share would be close to 0 if HP wasn't forcing everyone stuck on HP-UX or VMS to use them. Trust me, no one but HPC people (who aren't doing $/flop or watt/flop) are looking at them and saying "I really like what I see, so i'm going to get one and run my application on it".

I'm pretty darn familiar with HP-UX on IA, and I would take a good PA machine over anything with IA, any day of the week. The good news, is that this new processor might be fast enough to actually beat a 10 year old PA running PA binaries.

Re:Whytanium?

[mbessey]

I think your yield estimates are probably off by at least 2x, but that's not really important. Assuming your numbers are correct, a $1 Billion dollar money-maker is nothing to walk away from, even if it's "only" 4% to 8% of Intel's revenue.

I think continuing to develop Itanium would be worth it to Intel, even if they were to take a loss on it, year after year. A lot of the R&D effort that goes into making those monster chips, for example, will be directly applicable to future mass-market processors. The compiler technology is useful for massively-parallel future products from the Larrabee architecture line, etc, etc. Itanium serves as a test-bed, somewhere the designers and process engineers can try things that would be too risky in the mass-market products.

Obligatory car analogy: It's a little like how car companies produce limited-market enthusiast cars, and participate in racing. The Top-500 supercomputer list is computing's version of F1 racing.

Re:Whytanium?

[Patch86]

Oddly, I believe Ubuntu will do you full commercial support for UltraSPARC.

Slim pickings, admittedly, but still.

Re:Whytanium?

[VMSBIGOT]

I feel I should say something here, but not quite sure what

Re:Whytanium?

[evilviper]

Nobody Cares about Linux for enterprise platforms,

You got it completely backwards. A vastly more accurate description would be "nobody cares about proprietary platforms."

Linux support for most achitectures out there is pretty good. And in the past, Linux vendors supported many more platforms than they do now. Interest in Linux never declined... what happened is twofold.

1) AMD outflanked them all, and put together a spectacular 64-bit architecture, with a great implementation, and great backwards compatibilty.

2) Clustering solutions (software & off-the-shelf interconnects) have improved dramatically, and put clusters of commodity servers in the same class as mainframes. The lower cost, then, lead to a rapid usurping of the former leaders.

You need only take a look at the top500 list to see this fact. Linux is taking over, clusters are taking over, and x86-64 is taking over. Nobody cares about Linux on enterprise hardware because it's blindingly clear to all that enterprise hardware is dying, and nobody wants to jump into that sinking ship, unless they have expensive legacy apps, and Linux is too new to have much legacy, anyhow.

Just one thing...

[fuzzyfuzzyfungus]

Is it more resistant to icebergs than the previous itanics?

Re:Just one thing...

[gstoddart]

Is it more resistant to icebergs than the previous itanics?

This one melts right through them.

Re:Just one thing...

[JamesP]

Itanic 3: now sinking twice as fast!

Re:Just one thing...

[pleappleappleap]

Is it more resistant to icebergs than the previous itanics?

This one melts right through them.

And itself.

Re:Just one thing...

[Metabolife]

This one melts right through them.

So it melts right after hitting the iceberg? Impressive.

Re:Just one thing...

[alienzed]

and is twice as big!

Pity Pentiums can't be socket compatible

[Viol8]

Instead of everytime a new one comes along a new motherboard is required. Rather kicks any CPU upgrading possibilities into the long grass.

Re:Pity Pentiums can't be socket compatible

[Anonymous Coward]

Who knew that allowing a company to make both chipsets and processors would allow them to have such abuse of monopoly position as to force people to upgrade chipsets with every cpu upgrade?

Remind me again why Intel has 3 sockets for the same memory platform?

Re:Pity Pentiums can't be socket compatible

[Anonymous Coward]

I became a big AMD customer when they had their socket-A CPUs. The form factor ran a good long while, I was able to upgrade many times. Alas, AMD figured out that, like Intel, it is more profitable for them to force consumers to upgrade entirely, so without long-term socket support, I've migrated back to Intel (Core i7).
I'd like to see a company like "Evergreen", who used to make CPU upgrades, back in the market. It seems to me that a new 686-compatible CPU, with a fitting for a SO-DIMM to replace the L2 cache, and a set of adapter plates to accommodate various previous socket types, should have a decent-sized market. The adapter would emulate the proper ID String to allow the mainboard to boot, the SO-DIMM would keep the OS and software resident on the CPU (so to speak), virtually any old system could be made usable again.
Doesn't really jive with the customer-gouging mindset of modern North American business practice, though, does it. I'm sure there are a squadron of lawyers ready to beat back any entrepreneur wiling to go down that road.

Re:Pity Pentiums can't be socket compatible

[pleappleappleap]

AMD's processors still possess an upgrade path. I have no idea what you're talking about.

AM2->AM2+->AM3

I personally went from Windsor->Agena->Deneb without switching motherboard. Some time later, I upgraded my motherboard and kept my Deneb. I'm now thinking of upgrading my Deneb to a Thuban.

Re:Pity Pentiums can't be socket compatible

[Waffle Iron]

Given the nature of modern CPU bus specifications, your proposal would be so mechanically, electrically and logically complex that it would undoubtedly be cheaper just to buy a whole new computer system.

Re:Pity Pentiums can't be socket compatible

[Anonymous Coward]

Interesting, wasn't aware of the AM2 -> AM3 path. After Socket-A, AMD went S939, S940, & S754 (which I bought into), but then when another "all-new" socket (AM2?) came out, I looked elsewhere, never looked back.

Re:Pity Pentiums can't be socket compatible

[toddestan]

There were the relatively short-lived Sockets 754 and 939 before AMD went to AM2. Luckily for me, I jumped from Socket A straight to AM3, bypassing that nonsense.

On the other hand, Intel has had some relatively long lived sockets, like LGA775 which lasted from the later P4's up through the end of the Core 2's. That's about 4 years worth (and technically it's not dead yet as some of the Pentium Dual-Core chips are still in production). However, it's all kind of moot when they don't provide BIOS updates for their older boards to support the newer chips.

In other news....

[Anonymous Coward]

Itanium is somehow still relevant enough to warrant a "next generation" of it...

Ultimate Computer of Failure

[pezpunk]

ITANIC processor
RAMBUS memory
Voodoo5 video card
i can't think of a hard drive crappy enough ... maybe you could have the OS installed on an external drive connected via USB1.0.

obviously the OS would be WindowsME.

Re:Ultimate Computer of Failure

[VGPowerlord]

Any SATA drive with the Sandy Bridge SATA-2 controller?

Re:Ultimate Computer of Failure

[nschubach]

IBM/Hitachi Deskstar AKA: Deathstar

Re:Ultimate Computer of Failure

[StuartHankins]

I vote for Microsoft Bob as the OS.

Re:Ultimate Computer of Failure

[StuartHankins]

Ahh... and a Zip drive for backups! (Why didn't I think of that earlier?)

Re:Ultimate Computer of Failure

[imagoon]

Seagate (Quantum) Bigfoots

Re:Ultimate Computer of Failure

[voidphoenix]

Another vote for the Hitachi Deathstar. Heck, stripe a bunch together with RAID 0 for more lulz.

Re:Ultimate Computer of Failure

[Anonymous Coward]

Nah, the Voodoo5 was still good at running a lot of applications - the support just dried up and blew away when 3dfx did. Want the ultimate failure of video card design? Shove in a Volari V8 Duo Ultra.

Re:Ultimate Computer of Failure

[jpvlsmv]

IOmega "Click" drive for removable storage/backups. It was 40MB in a CF-card sized spinning disk.

--Joe

Re:Ultimate Computer of Failure

[Vectormatic]

vista would make it even slower then winME

and off course make those shitty IBM deathstar disks (i raid 0 as suggested) squeel in pain with all the indexing

Re:Ultimate Computer of Failure

[digitalsolo]

That's easy. Quantum Bigfoot 5.25" hard drives. They liked to randomly drop partition tables, when they worked at all.

Re:Ultimate Computer of Failure

[_merlin]

Funny thing is, I had a 60GB DeskStar, and it ran non-stop for eight years powering my router/DNS/proxy box. Did I just luck out, or was it a particular revision that had the issues?

Re:Ultimate Computer of Failure

[nschubach]

Oddly enough, I had an 80G that still ran up until about 6 months ago, but there were quite a few that failed. I remember that line though. It was around the time I worked in a repair shop and we sent a great many in for replacement.

Re:Ultimate Computer of Failure

[DurendalMac]

Nah. Zip was quite popular for a while. Zip750 would fit the bill, but not Zip in general. We're looking at things that were fails right from the start, and not just little indie products, but stuff from pretty big names at the time.

Re:Ultimate Computer of Failure

[DurendalMac]

This. The Voodoo5 wasn't as popular as earlier cards by 3dfx and was released as they fell behind, but it wasn't a bad card and still ran fine. It just wasn't enough to save them. Very sad. Oh 3dfx...

Re:Ultimate Computer of Failure

[drinkypoo]

Better option: Anything from Conner Peripherals.

Re:Ultimate Computer of Failure

[Anonymous Coward]

Quantum Bigfoot?

Re:Ultimate Computer of Failure

[CAIMLAS]

Quantum Bigfoot: the name itself defies parody. It was that bad.

Re:Ultimate Computer of Failure

[Anonymous Coward]

Quantum Fireball: no nickname required.

it's ititanic 2

[Joe The Dragon]

it's ititanic 2

Isn't it strange...

[ColonelClaw]

...how Intel can make an all-new architecture socket-compatiable with the previous generation for an enterprise product that no-one's interested in, yet they can't manage this with their consumer products? e.g. Sandy Bridge. It's almost as if they're taking advantage of their market dominance by screwing us all over!

Re:Isn't it strange...

[gstoddart]

It's almost as if they're taking advantage of their market dominance by screwing us all over!

Eerie, isn't it?

Re:Isn't it strange...

[RyuuzakiTetsuya]

AFAIK, Sandy Bridge includes a GPU on die. So, of course it's going to need more interconnects.

The market for enthusiast boards is pretty small for intel, especially when you consider the sheer volume of low end crap fests OEMs plop out a year. I don't think they're trying to screw their OEM partners as the cost per-unit is probably pretty small.

I'm just curious how this is any better than integrating the GPU into the chipset.

Re:Isn't it strange...

[sexconker]

It's almost as if they're taking advantage of their market dominance by screwing us all over!

Eerie, isn't it?

Well, when you've got Superior products, you tend to fuck everyone over.
Though AMD's Ontario got out of the gate before Intel's Huron platform and is in fact, better.
AMD's been successfully focusing on the segment they can compete in for a while now - the auto makers in Michigan could learn a few things from AMD.

Re:Isn't it strange...

[Olivier Galibert]

That's because the high-end server world accepts level of single-core performance the consumer world doesn't. These processors are not something you want on your PC. You want something with better memory management, way faster I/O with ram and GPU, etc. OTOH, you usually don't care about multi-processor.

But faster I/O usually means putting more things on the die (hence amd's integrated memory controllers, now followed by Intel) and having larger busses/more efficient protocols, and acting on that means changing the socket. And the north bridge, if one is left. And the memory, for a faster one. You wouldn't get enough speedup from changing the cpu alone with everything else pin-compatible to make it worth it.

Meanwhile, the itanic spends its time waiting for the ram to answer... but since you put a lot of them in the box, in aggregate they can be useful.

    OG.

Re:Isn't it strange...

[Anonymous Coward]

Thanks to advances in the integrated memory platforms that AMD started way back in 2005 and Intel finally started in 2008 there is no proper north bridge any more. The memory is controlled by the CPU, so in a world where memory throughput actually mattered for integrated video you'd have significantly better performance.

Re:Isn't it strange...

[Anonymous Coward]

No, just no

Re:Isn't it strange...

[Anonymous Coward]

auto-industry competition? pfft. No such thing. Why would they want one arm of the company to compete against the other arm, when they are use the same designs for both and make minor differences then sell one for a "normal" profit and the others for a "great" profit?

As an example, a Lexus is just a larger Toyota with more leather, or using my car which has at least 2 other models based on the same frame from companies under GM.

Re:Isn't it strange...

[Anonymous Coward]

Westmere also had a GPU on die.

Re:Isn't it strange...

[Anonymous Coward]

That's because the high-end server world accepts level of single-core performance the consumer world doesn't. These processors are not something you want on your PC. You want something with better memory management, way faster I/O with ram and GPU, etc. OTOH, you usually don't care about multi-processor.

Tell this to the POWER and Z folks, for example. They die laughing. Even the elusive SPARC tribe might join in.

Re:Isn't it strange...

[Anonymous Coward]

It was 2003 for AMD, not 2005.

What MoJoKid, own Intel Stock???

[rubycodez]

That's a funny line you wrote their "sheds the last vestiges of negativity". Microsoft has dumped Itanium since 2008 R2, Redhat has dumped Itanium for RHEL 6, the only things left are niche markets for HP/UX (market share plummeting as you read this, being eaten alive by IBM PPC / Z series), OpenVMS (well hello mid 1980s and early 90s), and NonStop (neat in its day too, but again IBM eating its lunch) The ship Itanic continues to auger into the ocean floor.

Re:What MoJoKid, own Intel Stock???

[the linux geek]

Oh, please. Unlike Power, which if you look at the sales numbers has had an awful few months, Itanium is doing pretty damn well. $4bn to $5bn with reliable growth (feeding off Oracle's neglect of M-series SPARC) is a good place to be. Additionally, if Poulson came out today, it would probably be the fastest processor in the world (4-6x the raw performance of the Itanium 9300 should put it slightly ahead of Power7).

Re:What MoJoKid, own Intel Stock???

[raftpeople]

Additionally, if Poulson came out today, it would probably be the fastest processor in the world (4-6x the raw performance of the Itanium 9300 should put it slightly ahead of Power7).

Ok. So you are telling me that today, Power7 is almost 4-6x the raw performance of Itanium 9300? But if we wait until the end of 2012 or early 2013 when Poulson ships, it will be slightly ahead of today's Power7?

Are you trying to help or hurt Itanium with this info?

Re:What MoJoKid, own Intel Stock???

[the linux geek]

Poulson is likely to ship Q1 of 2012, shortly before IBM's Power7+ refresh is likely. It'll be competitive enough, especially if P7+ is a shitty refresh like P6+ was. (It had slightly improved power characteristics and no performance enhancements.)

Re:What MoJoKid, own Intel Stock???

[operagost]

You really think that VMS hasn't been developed since the 1990s?

Re:What MoJoKid, own Intel Stock???

[Anonymous Coward]

Wow, $5 billion...

... so what's that then, like 20 chips?

Re:What MoJoKid, own Intel Stock???

[raftpeople]

Why do you think Poulson will ship in Q1 of 2012? I don't remember if any Itaniums have shipped on time, but I definitely remember multiple not shipping on time.

Here's a recent refresher: Tukwilla specs released early 2008 which had an initial ship estimate of Q42008, actual ship Q12010

Re:What MoJoKid, own Intel Stock???

[Dputiger]

Ruby, Not sure what you're referring to here. I'm the original author of the piece. I'm most definitely not MojoKid.

Re:What MoJoKid, own Intel Stock???

[SharpNose]

I worked with VMS for a total of about seven years, up to 1999. There are things about it that make *ix look positively quaint, starting with the filesystem. I doubt I'll have occasion to work with it again, but someone who chose to make VMS the basis of a modern operation could do a hell of a lot worse.

Re:What MoJoKid, own Intel Stock???

[Anonymous Coward]

Actually P7+ is likely to ship before the end of the year (typical IBM cycle is 18 months, and P7 started shipping in February last year).

Given the typical Itanium delays, it would be more or less simultaneous with Power8 (early 2013).

Re:What MoJoKid, own Intel Stock???

[rubycodez]

You're ignoring the other power-derived thing, the mainframes (which HP Integrity tries to compete) so we're talking IBM's $5 + $5 billion vs. Itaniums $5 billion oh please indeed, Itanic is going down the crapper.

Re:What MoJoKid, own Intel Stock???

[rubycodez]

no, I believe the only shops with OpenVMS now are those that had it back then. No one is going to roll out new system based on VMS. It's not a growth market, it's a ride-the-horse-until-it-dies one. It's something clients should be migrated off if they are forward-looking.

Re:What MoJoKid, own Intel Stock???

[rubycodez]

I was a VMS sys admin back in the day, but ODS-5 really doesn't do anything that modern Unix filesystems can't do - shadow sets for replication, volume sets, shared in cluster, hard links,

Re:What MoJoKid, own Intel Stock???

[rubycodez]

The page I load says MojoKid submitted the story, CmdrTaco post it

It's socket-compatible with the older Tukwila proc

[sexconker]

"It's socket-compatible with the older Tukwila processors."

But the desktop market?
My oh my, that's impossible!
See, we've added a single extra pin, and I'm afraid you have no choice but to buy a new motherboard if you want a new CPU, or vice versa.

'V'+1, 'M'+1, 'S'+1 ?

[mevets]

Were there features left out?

In other news...

[Anonymous Coward]

...the Ford motor company announces the new 2012 Edsel.

Re:In other news...

[pleappleappleap]

I'd buy that shit. The only thing that would lure me away from it would be a 2012 Pinto!

Re:In other news...

[bobv-pillars-net]

I loved my Pinto. I *miss* my Pinto.

Re:In other news...

[Vegemeister]

I still have mine.

Marketing at it finest

[ThePhilips]

It may also be the Itanium that fully redeems the brand name and sheds the last vestiges of negativity that have dogged the chip since it launched ten years ago. Poulson incorporates a number of advances in its record-breaking 3.1 Billion transistors. It's socket-compatible with the older Tukwila processors and offers up to eight cores and 54MB of on-die memory.

That is so ridiculous that it is not funny.

Biggest complain about Itanic was always absence of cheap versions, something companies can put on engineer' desks.

Seeing what people do around AMD64 architecture, I doubt Itanic would ever become mainstream - it would remain forever a pet platform of HP's service unit. Similar to IBM's POWER: something sufficiently incompatible so that customers can't migrate overnight to competitor's platform.

Re:Marketing at it finest

[VolciMaster]

It may also be the Itanium that fully redeems the brand name and sheds the last vestiges of negativity that have dogged the chip since it launched ten years ago. Poulson incorporates a number of advances in its record-breaking 3.1 Billion transistors. It's socket-compatible with the older Tukwila processors and offers up to eight cores and 54MB of on-die memory.

That is so ridiculous that it is not funny.

Biggest complain about Itanic was always absence of cheap versions, something companies can put on engineer' desks.

Seeing what people do around AMD64 architecture, I doubt Itanic would ever become mainstream - it would remain forever a pet platform of HP's service unit. Similar to IBM's POWER: something sufficiently incompatible so that customers can't migrate overnight to competitor's platform.

Yes, HPUX is the only major OS for the platform in the West - but (so I've heard from Intel sales and engineering folks) Japan (specifically Fujitsu) buys a lot of these things. So do some major companies in the US - but they also write their own applications/OSes for the platform (ie, they're NOT running HPUX on it).

Re:Marketing at it finest

[Dputiger]

ThePhilips, According to Intel, Poulson incorporates redesigned FPU and ALU structures, as well as the 12-issue design (which I admit in the article may not really be a good thing from a code optimization standpoint). It's impossible to currently gauge the compiler improvements Intel may introduce when the chip launches *or* the value of the ALU/FPU pipeline. You seem to have missed my point that Itanium was badly mis-marketed; it's partly seen as a failure precisely because it was pushed as a next-generation solution for all sorts of systems it should never have been positioned to fulfill. If we *start* from the position that Intel would retrench the chip's marketing more neutrally, then I think my statement is quite accurate.

Re:Marketing at it finest

[ebh]

Not surprising that Fujitsu is still in the act, since some of their people were involved (as in on-site at HP's Florham Park lab where I worked) when the original compiler and HP-UX port were being developed. Closing that site and laying us all off didn't speak well for HP's nascent world-changer.

Re:Marketing at it finest

[the linux geek]

Yeah, outside the US, Itanium is big on mainframes. Fujitsu, NEC, Bull, and (I think) Hitachi all run proprietary mainframe OS's on IA64, and at least in their home countries they do a pretty good business.

run-time?

[cfriedt]

"Itanium relies on the compiler to optimize code at run-time."

I definitely would NOT buy an Itanium unless they change the compiler to optimize code at compile-time.

Re:It's socket-compatible with the older Tukwila p

[Ant P.]

If that's the case then you're buying desktop CPUs from the wrong vendor.

Get off my front lawn.

[Anonymous Coward]

You're not gettin' in.

A timeless story

[Un pobre guey]

Diving beneath the settling chip fab, the Itanium ran quivering along its keel; but turning under water, swiftly shot to the surface again, far off the other bow, but within a few yards of HP's boat, where, for a time, it lay quiescent.

"I turn my body from the sun. What ho, Tashtego! let me hear thy hammer. Oh! ye three unsurrendered spires of mine; thou uncracked keel; and only god-bullied hull; thou firm deck, and haughty helm, and Pole-pointed prow,- death- glorious chip fab! must ye then perish, and without me? Am I cut off from the last fond pride of meanest CPU Product Managers? Oh, lonely death on lonely life! Oh, now I feel my topmost greatness lies in my topmost grief. Ho, ho! from all your furthest bounds, pour ye now in, ye bold billows of my whole foregone life, and top this one piled comber of my death! Towards thee I roll, thou all-destroying but unconquering Itanium; to the last I grapple with thee; from hell's heart I stab at thee; for hate's sake I spit my last breath at thee. Sink all coffins and all hearses to one common pool! and since neither can be mine, let me then tow to pieces, while still chasing thee, though tied to thee, thou damned Itanium! Thus, I give up the spear!"

The harpoon was darted; the stricken Itanium flew forward; with igniting velocity the line ran through the surface mounts;- ran foul. HP stooped to clear it; they did clear it; but the flying turn caught them round the neck, and voicelessly as Turkish mutes bowstring their victim, they were shot out of Palo Alto,' ere all the Valley knew they were gone. Next instant, the heavy eye-splice in the rope's final end flew out of the stark-empty tub, knocked down an oarsman, and smiting the sea, disappeared in its depths.

For an instant, the tranced crew stood still; then turned. "The chip fab? Great God, where is the chip fab?" Soon they through dim, bewildering mediums saw its sidelong fading phantom, as in the gaseous Fata Morgana; only the uppermost floors out of water; while fixed by infatuation, or fidelity, or fate, to their once lofty perches, the pagan Marketing Staff still maintained their sinking look-outs on the CPU market. And now, concentric circles seized the lone fab itself, and all its crew, and each floating oar, and every lancepole, and spinning, animate and inanimate, all round and round in one vortex, carried the smallest chip of Hewlett-Packard out of sight.

Re:It's socket-compatible with the older Tukwila p

[petermgreen]

Well there are really two choices for desktop CPUs, AMD and Intel.

AMDs next gen of CPUs (bulldozer) will apparently not work in existing boards. Sandy bridge is pretty much ruled out (unless you are a masochist) by the recall. So whichever side of the fence you go for right now you will most likely be buying into a dying socket.

R&D for Xeons

[Anonymous Coward]

Itanium is a platform for Intel's R&D. Hello NehalemEX.

LLVM and Itanium?

[Gary W. Longsine]

I hate to break up a good pizza party, but I've been wondering if LLVM and Clang might help rescue Itanium as hinted by this 2005 paper which suggests a few compiler enhancements to help Itanium.

Re:LLVM and Itanium?

[TheRaven64]

Nope, I also hack on LLVM. The LLVM Itanium back end is more or less unmaintained at the moment (unless someone's picked it up recently). It has very poor performance. It might even be worse than GCC - LLVM's IR is not an especially good match for EPIC (or even classic VLIW), so the instruction selection phase has to do a massive amount of work. This is usually a simple pattern matching exercise, but for Itanium it's incredibly complex to do well.

Re:LLVM and Itanium?

[turgid]

I just did a google for "open source itanium emulator" and found this thing called ski which is allegedly an IA64 instruction set simulator, originally developed by HP and released under the GPL.

I wonder would it be possible to hack together an itanium emulator from this code that would achieve or surpass native itanium performance on cheap x86-64 hardware? Multi-core/multi-CPU x86-64 boxes are so cheap these days that price/performance wise, we can't be far off.

Announcing 5 trillion digits of Pi!

[epine]

APL rocks when your floating point addition latency exceeds your main memory fetch latency and your programmers don't mind that the trig operators are selected by manifest constants on the left side of the circle operator.

Itanium is trying to fit the niche where SIMD is not applicable, yet arithmetic instruction density is high relative to memory transactions.

I spent too much time last night reading about big constants. y-cruncher is sick. It's also not open source, and the core algorithm (Hybrid NTT multiplication, which finds a nice niche between FFT and SS) hasn't been published. There are, however, some highly-tuned Linux binaries for common architectures.

Announcing 5 trillion digits of Pi!

From the FAQ:

Unlike the majority of compute-intensive applications, y-cruncher does not exclusively use floating-point. As of v0.5.4, only about 30% of a Pi computation is floating-point bound. The remainder of the time is spent on integer operations and stalling on memory access. [my bold] So cutting that 30% in half yields little overall speedup. Speeding up the code in this manner exposes more memory bottlenecks - which ends up reducing the speedup to only 10%...

Integer operations can be largely be emulated using floating-point (albeit with overhead). But most of the integer work involves carry-propagation, so it is not very vectorizable. For now, integer operations are still faster using the normal integer instructions.

I'm sure the program would find some love the 54MB on-chip cache, but the Itanium instruction set would only be a burden, and stalls would be horrendous.

Why does y-cruncher create more threads than I tell it to use?

[] Because of the nature of some of the algorithms, I find it necessary to spam threads in order to maximize multi-core efficiency.

The cool thing about this program is that it scales nearly linearly in number of cores, and overscheduling doesn't impact it much if the aggregate memory bandwidth can be supported.

Can you make a CUDA version?

The memory bandwidth between the GPU and main memory will almost certainly be a bottleneck. This isn't a problem for small computations that will fit entirely into GPU memory, but small computations isn't the point of y-cruncher.

Cancel the love for 54MB of on-chip cache. That about cancels the love for the entire architecture. What might rescue the iBerg someday is an optical memory interconnect, if they're looking to blow another $4b burning a hole in the other pocket.

Re:Announcing 5 trillion digits of Pi!

[sznupi]

What might rescue the iBerg someday is an optical memory interconnect, if they're looking to blow another $4b burning a hole in the other pocket.

No reason, really? Itanium seems to have done its job - killing virtually every other "heavyweight" architecture (and IBM wouldn't cancel theirs "in anticipation of new great thing from Intel", anyway)

just catching up....

[prowler]

to IBM's PowerPC processors

Itanium instruction widths

[John Bayko]

Since the instruction format hasn't changed (still using 6 instruction bundles), I think Poulson is just ignoring the packing info and being superscalar just like every other high performance chip (Alpha EV6 or EV7 (can't remember) and Power 4 grouped instructions internally, rather than flinging them independently through the execution units - simplified tracking, apparently). Actually I think even the previous version of Itanium gave up on that - runtime data lets you group independent instructions more efficiently anyway, so many people thought it was a waste of time to try to get the compiler to do it when Itanium was introduced. Remember, it was not the first, but the last of a long history of attempts at making VLIW not suck (er. except Transmeta, which doesn't count because it hid the native instructions - essentially it put the instruction grouping into software rather than hardware, and that was never fast enough to work well).

Still, recompiling could make runtime grouping better, so you'd get more speedups if you did. But even existing binaries should benefit.

Re:Itanium instruction widths

[sznupi]

Fundamentally, it was probably an attempt to help cancellations of other "heavyweight" architectures. At that it performed admirably (and for Intel it doesn't make too much difference if the shift ended up being to x86)

Poulson? Poulsbo?

[Anonymous Coward]

Anyone see a parallel here? & I'm not just talking about the name.

Intel can't produce a decent performance low-volt gpu, so they buy something then don't release the specs so a good OSS driver can be produced & maintained. Ref Poulsbo. Way to go, uber-chip-lord!

It appears Poulson has about as wonderful a reputation.

Oh well...