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Intel Unveils Next Gen Itanium Processor
MojoKid writes "This week, at ISSCC Intel unveiled its next-generation Itanium processor, codenamed Poulson. This new design is easily the most significant update to Itanium Intel has ever built and could upset the current balance of power at the highest-end of the server / mainframe market. It may also be the Itanium that fully redeems the brand name and sheds the last vestiges of negativity that have dogged the chip since it launched ten years ago. Poulson incorporates a number of advances in its record-breaking 3.1 Billion transistors. It's socket-compatible with the older Tukwila processors and offers up to eight cores and 54MB of on-die memory."
Guess the guys at Intel have been watching Fight Club a little too much.
Gonzo Granzeau
"Nothing the god of biomechanics wouldn't let you into heaven for.." -Roy Batty
Does anyone else cringe when they here Itanium? The early chips still give me nightmares.
"A person is smart. People are dumb, panicky dangerous animals and you know it." - K
Seeing as how Itanium has already failed at its core objective, why is Intel continuing to push it?
Is it just a guilty conscience over coercing HP into dumping Alpha?
Is it more resistant to icebergs than the previous itanics?
Instead of everytime a new one comes along a new motherboard is required. Rather kicks any CPU upgrading possibilities into the long grass.
Oh, but MIPS are still being used commonly. http://www.mips.com/
I'm starting to think GNU is the problem with "GNU/Linux" these days.
ITANIC processor ... maybe you could have the OS installed on an external drive connected via USB1.0.
RAMBUS memory
Voodoo5 video card
i can't think of a hard drive crappy enough
obviously the OS would be WindowsME.
i could live a little longer in this prison
it's ititanic 2
...how Intel can make an all-new architecture socket-compatiable with the previous generation for an enterprise product that no-one's interested in, yet they can't manage this with their consumer products? e.g. Sandy Bridge. It's almost as if they're taking advantage of their market dominance by screwing us all over!
That's a funny line you wrote their "sheds the last vestiges of negativity". Microsoft has dumped Itanium since 2008 R2, Redhat has dumped Itanium for RHEL 6, the only things left are niche markets for HP/UX (market share plummeting as you read this, being eaten alive by IBM PPC / Z series), OpenVMS (well hello mid 1980s and early 90s), and NonStop (neat in its day too, but again IBM eating its lunch) The ship Itanic continues to auger into the ocean floor.
Were there features left out?
It may also be the Itanium that fully redeems the brand name and sheds the last vestiges of negativity that have dogged the chip since it launched ten years ago. Poulson incorporates a number of advances in its record-breaking 3.1 Billion transistors. It's socket-compatible with the older Tukwila processors and offers up to eight cores and 54MB of on-die memory.
That is so ridiculous that it is not funny.
Biggest complain about Itanic was always absence of cheap versions, something companies can put on engineer' desks.
Seeing what people do around AMD64 architecture, I doubt Itanic would ever become mainstream - it would remain forever a pet platform of HP's service unit. Similar to IBM's POWER: something sufficiently incompatible so that customers can't migrate overnight to competitor's platform.
All hope abandon ye who enter here.
I'd buy that shit. The only thing that would lure me away from it would be a 2012 Pinto!
SGI isn't making MIPS chips, but a lot of other companies are. As I said in another post, I sometimes work with a company that produces compilers for HPC, and they are seeing a lot more demand for MIPS than for Itanium. A lot of interesting processors are using the MIPS instruction set. It's cheap to license, so companies wanting to do things like put 64 cores on a chip just license MIPS. There's also the Chinese version, which is starting to look quite respectable - especially in price/performance metrics.
I am TheRaven on Soylent News
"Itanium relies on the compiler to optimize code at run-time."
I definitely would NOT buy an Itanium unless they change the compiler to optimize code at compile-time.
I loved my Pinto. I *miss* my Pinto.
The Web is like Usenet, but
the elephants are untrained.
If that's the case then you're buying desktop CPUs from the wrong vendor.
Diving beneath the settling chip fab, the Itanium ran quivering along its keel; but turning under water, swiftly shot to the surface again, far off the other bow, but within a few yards of HP's boat, where, for a time, it lay quiescent.
"I turn my body from the sun. What ho, Tashtego! let me hear thy hammer. Oh! ye three unsurrendered spires of mine; thou uncracked keel; and only god-bullied hull; thou firm deck, and haughty helm, and Pole-pointed prow,- death- glorious chip fab! must ye then perish, and without me? Am I cut off from the last fond pride of meanest CPU Product Managers? Oh, lonely death on lonely life! Oh, now I feel my topmost greatness lies in my topmost grief. Ho, ho! from all your furthest bounds, pour ye now in, ye bold billows of my whole foregone life, and top this one piled comber of my death! Towards thee I roll, thou all-destroying but unconquering Itanium; to the last I grapple with thee; from hell's heart I stab at thee; for hate's sake I spit my last breath at thee. Sink all coffins and all hearses to one common pool! and since neither can be mine, let me then tow to pieces, while still chasing thee, though tied to thee, thou damned Itanium! Thus, I give up the spear!"
The harpoon was darted; the stricken Itanium flew forward; with igniting velocity the line ran through the surface mounts;- ran foul. HP stooped to clear it; they did clear it; but the flying turn caught them round the neck, and voicelessly as Turkish mutes bowstring their victim, they were shot out of Palo Alto,' ere all the Valley knew they were gone. Next instant, the heavy eye-splice in the rope's final end flew out of the stark-empty tub, knocked down an oarsman, and smiting the sea, disappeared in its depths.
For an instant, the tranced crew stood still; then turned. "The chip fab? Great God, where is the chip fab?" Soon they through dim, bewildering mediums saw its sidelong fading phantom, as in the gaseous Fata Morgana; only the uppermost floors out of water; while fixed by infatuation, or fidelity, or fate, to their once lofty perches, the pagan Marketing Staff still maintained their sinking look-outs on the CPU market. And now, concentric circles seized the lone fab itself, and all its crew, and each floating oar, and every lancepole, and spinning, animate and inanimate, all round and round in one vortex, carried the smallest chip of Hewlett-Packard out of sight.
Well there are really two choices for desktop CPUs, AMD and Intel.
AMDs next gen of CPUs (bulldozer) will apparently not work in existing boards. Sandy bridge is pretty much ruled out (unless you are a masochist) by the recall. So whichever side of the fence you go for right now you will most likely be buying into a dying socket.
note: i'm known as plugwash most places but i screwd up registering that here somehow in the past and now can't register
The company I work for makes 64-bit MIPS processors with up to 16 cores (soon 32 cores). They're optimized for I/O, networking, storage and security and lack floating point though. The nice thing with MIPS is that it's easy to extend the instruction set without breaking anything. We've added a number of instructions and have extended gcc/binutils to take advantage of it. And yes, they all run Linux.
Being a traditional RISC type platform makes it not too difficult for the compiler to optimize code for.
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I hate to break up a good pizza party, but I've been wondering if LLVM and Clang might help rescue Itanium as hinted by this 2005 paper which suggests a few compiler enhancements to help Itanium.
If you mod me down, I shall become more powerful than you could possibly imagine.
We've added a number of instructions and have extended gcc/binutils to take advantage of it.
And this is the bit that makes so many people hate MIPS. Every vendor has their own GCC / binutils fork, often based on an old version, with patches that can't be pushed upstream without breaking other architectures.
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Actually ours is in the mainline gcc, so there's no special fork unless you want the bleeding edge support, which always takes a little while to get checked in to the main branch.
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The MIPS architecture is alive and well from the looks of things, and not just in the realm of HPC, and it is probably the most popular RISC CPU architecture in history. I carry such a processor around with me every day in the form of a CXD2962GG CPU in my Sony PlayStation Portable, which is essentially a clone of the MIPS R4000. The PSX used a MIPS R3000-family CPU that was essentially the same as what you would find inside an old SGI Indigo. Apparently the PS2's Emotion Engine was actually a MIPS III/IV architecture CPU with extra SIMD instructions similar to Intel's MMX/SSE. I imagine that MIPS-architecture processors are even more common in embedded systems.
Qu'on me donne six lignes écrites de la main du plus honnête homme, j'y trouverai de quoi le faire pendre.
APL rocks when your floating point addition latency exceeds your main memory fetch latency and your programmers don't mind that the trig operators are selected by manifest constants on the left side of the circle operator.
Itanium is trying to fit the niche where SIMD is not applicable, yet arithmetic instruction density is high relative to memory transactions.
I spent too much time last night reading about big constants. y-cruncher is sick. It's also not open source, and the core algorithm (Hybrid NTT multiplication, which finds a nice niche between FFT and SS) hasn't been published. There are, however, some highly-tuned Linux binaries for common architectures.
Announcing 5 trillion digits of Pi!
From the FAQ:
Unlike the majority of compute-intensive applications, y-cruncher does not exclusively use floating-point. As of v0.5.4, only about 30% of a Pi computation is floating-point bound. The remainder of the time is spent on integer operations and stalling on memory access. [my bold] So cutting that 30% in half yields little overall speedup. Speeding up the code in this manner exposes more memory bottlenecks - which ends up reducing the speedup to only 10%...
Integer operations can be largely be emulated using floating-point (albeit with overhead). But most of the integer work involves carry-propagation, so it is not very vectorizable. For now, integer operations are still faster using the normal integer instructions.
I'm sure the program would find some love the 54MB on-chip cache, but the Itanium instruction set would only be a burden, and stalls would be horrendous.
Why does y-cruncher create more threads than I tell it to use?
[] Because of the nature of some of the algorithms, I find it necessary to spam threads in order to maximize multi-core efficiency.
The cool thing about this program is that it scales nearly linearly in number of cores, and overscheduling doesn't impact it much if the aggregate memory bandwidth can be supported.
Can you make a CUDA version?
The memory bandwidth between the GPU and main memory will almost certainly be a bottleneck. This isn't a problem for small computations that will fit entirely into GPU memory, but small computations isn't the point of y-cruncher.
Cancel the love for 54MB of on-chip cache. That about cancels the love for the entire architecture. What might rescue the iBerg someday is an optical memory interconnect, if they're looking to blow another $4b burning a hole in the other pocket.
I still have mine.
to IBM's PowerPC processors
Since the instruction format hasn't changed (still using 6 instruction bundles), I think Poulson is just ignoring the packing info and being superscalar just like every other high performance chip (Alpha EV6 or EV7 (can't remember) and Power 4 grouped instructions internally, rather than flinging them independently through the execution units - simplified tracking, apparently). Actually I think even the previous version of Itanium gave up on that - runtime data lets you group independent instructions more efficiently anyway, so many people thought it was a waste of time to try to get the compiler to do it when Itanium was introduced. Remember, it was not the first, but the last of a long history of attempts at making VLIW not suck (er. except Transmeta, which doesn't count because it hid the native instructions - essentially it put the instruction grouping into software rather than hardware, and that was never fast enough to work well).
Still, recompiling could make runtime grouping better, so you'd get more speedups if you did. But even existing binaries should benefit.