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IBM, 3M Team To Glue Together Silicon "Bricks"
coondoggie writes "IBM and 3M today said they will jointly develop a new line of adhesives they hope will let them make it possible to build commercial microprocessors composed of layers of up to 100 separate chips. Such stacking would allow for higher-powered servers and more advanced consumer electronics applications, the companies stated. Processors could be tightly packed with memory and networking, for example, into a 'brick' of silicon that would create a computer chip 1,000 times faster than today's fastest microprocessor enabling more powerful smartphones, tablets, computers and gaming devices."
Hmmm
"The greatest lesson in life is to know that even fools are right sometimes" - Winston Churchill
Stacking these things is all well and good, but at what point do heat considerations become a primary concern? Lately I haven't gotten the impression that volume of ICs is our biggest bottleneck.
--
That is going to be fun to cool...
I wouldn't be surprised if there are some specialty niche application guys who are just drooling at the prospect of vastly increased silicon area without more board space or interconnect hassle; but anybody who is cranking the clock, the power handling, or both, is going to find the utility of the layers at the center a bit dubious.
100 more ways to brick a machine.
Stacking these things is all well and good, but at what point do heat considerations become a primary concern? Lately I haven't gotten the impression that volume of ICs is our biggest bottleneck.
The article indicates that heat is already a primary concern. 3M's role in the endeavor is to develop adhesives with good thermal conductivity.
remember the CPU chip for the Terminators? it was more brick-like than chip-like...
hmmmm
I'm sure I'm one of thousands of folks thinking that how to glue together chips must be the least concern, and how to dissipate heat must be the highest?
The only thing I can think of that makes the adhesive important would be how well it holds up under heat, so maybe thats why its hard to do?
I imagine such a "brick" of silicon would probably have to have active cooling build into it, such as etched-in heat pipes or even some kind of micro fluid cooling system. Thats where the interesting stuff is happening.
I mean, really.. glue.. how exciting is that?
-- Senior Software Engineer, Attorney appearance services, locallawyerapp.com.
Three possibilities:
1) Moore's Law broken
2) This won't see the light of day for a LONG time
C) They are exaggerating.
She's a brick house
Mighty might just lettin it all hang out
She's a brick house
The lady's stacked and that's a fact
Ain't holding nothing back
She's a brick house
She's the one, the only one
Who's built like a amazon
We're together everybody knows
And here's how the story goes
She knows she got everything
A woman needs to get a man yeah
How can she lose with what she use
36-24-36 what a winning hand !!
The clothes she wears, the sexy ways
Make an old man wish for younger days
She knows she's built and knows how to please
Sure enough to knock a man to his knees
Shake it down, shake it down now !!
>> enabling more powerful smartphones, tablets, computers and gaming devices." So we can expect any battery powered device to last for 4 mins, compared to the 4 hours one can expect from a dual core mobile phone?
These chips already exist, and have since the start of IC's. Its called embedded chips... take a core (or 8), put it on a XBAR bus with a bunch of peripherals, flash and SRAM, and you've got yourself a minicomputer... that has ADC's... and is the size of your thumbnail
Isn't this story a little vaporwarish? The companies "hope to develop" these new techniques and materials. There's no mention of an underlying discovery which the two companies might help each other commercialize. There's just this idea -- "Gee, wouldn't it be cool if we could do this? Let's look into it!" Is this actually news yet?
"Imaginary solutions to real problems."
Advantages: speed- Total execution time is based on distance the signal must travel- vertical stacking shortens distance. space- having half your motherboard used up for ram limits what you can do. If you ever want to see TB usb sticks you need this. Board space in a cellphone is very limited, with this you can multiply the number of chips on the board by 10/20/30 depending on how thin the slices are. cooling: you can etch channels on the backside before you glue to run cooling oil through.
You are repeating Khan's failure, you are thinking in 2D not 3D. Oh wait, Khan's failure occurs in future so I guess you are not repeating it. ;-)
On a more serious note we are simply repeating historical urban development. When land was plentiful we tended build out horizontally rather than vertically, I guess the building technology and materials also contributed to this (as it also apparently does in semiconductors). However when land started to become a scarce resource then we started to build vertically. At some point if we want to keep that IC at the size of a thumbnail we will need to go vertical as well.
These things will generate some heat, no doubt.
for 20 years.
The fact that today's chip processing is all 2d and was bound to change for 3d at some point comes as no surprise to some I'm sure.
Use it to secure your Christmas presents!
A reference for some readers: http://en.wikipedia.org/wiki/Three-dimensional_integrated_circuit
"Power – Keeping a signal on-chip can reduce its power consumption by 10-100 times. Shorter wires also reduce power consumption by producing less parasitic capacitance. Reducing the power budget leads to less heat generation, extended battery life, and lower cost of operation."
"Heat – Heat building up within the stack must be dissipated. This is an inevitable issue as electrical proximity coorrelates with thermal proximity. Specific thermal hotspots must be more carefully managed."
A stack of Pentiums, attached with 3M Scotch 665 double sided adhesive tape.
1) "Standard" solution is to interleave copper fins between chiplets to take heat out -- and yes, it has been major problem for 3D integration.
2) Of course it's Intel and 3M, but do not think that this is new at all -- at my previous place of employment (6 years ago) we have been working with these guys: http://www.irvine-sensors.com/r_and_d.html#Neo-Stack -- and they have this technology for quite some time before that.
Interesting tidbit I've heard from their CTO (I think): if you take a full height rack of electronics, total active volume of all transistors and metal wires on all the chips inside is about 1 cm^3...
But yes, taking heat out is a problem.
Paul B.
Find some super-thermally conductive material, punch holes through the new bricks in several places (planning ahead of time to avoid stuff like, oh, circuits), place or thread the material into the holes and do a quick compress to ensure it fills up the hole and touches the entire length. Then connect the outside part of the conductor to whatever cheaper heat sink you want. Even if the inner conductor material is expensive at least it transfers the heat outside and away from the inner core.
It would be even neater if the interfacing between the chips was incorporated into the sides of the holes somehow.
This article is a bit deceptive. IBM is not trying to create a package with 1000 high-end, high-power CPUs in it. Clearly, this would require 1000 times the thermal capacity in the cooling system, not to mention 40kW power supply to drive it and a pair of 40kA copper rails to bring all that current (at 1V) into and out of the package. This is not happening. The issue IBM is looking at is silicon defects. If you make a single MIPS processor per die, then you can get 10,000 of them on a wafer. If that wafer suffers 100 random defects, then you still have 9900 good die for 99% yield. However, if you try to make 64-core processors that are fashionable today then you only have 156 units on your wafer and the same 100 defects leave you with only 56 prime dice, for 36% yield which is shit. IBM's big idea seems to be to manufacture the multi-core processors which can be assembled from a multiplicity of known good die. They aim to build 64-core CPUs, by stacking tiny single-core CPUs, not the 64000-core CPUs that I pictured when reading this article.
"1,000 times faster than today's fastest microprocessor enabling more powerful smartphones, tablets, computers and gaming devices."
AKA
"1,000 times faster than today's fastest microprocessor enabling the devices to run even more layers of encapsulation, virtual machine languages, and scripting crap at the same speed our computers operate today".
Board space in a cellphone is very limited, with this you can multiply the number of chips on the board by 10/20/30 depending on how thin the slices are.
But how many of these chips will be used for adding functionality, as opposed to adding measures to restrict the owner of a phone from making full use of the functionality? Case in point: the PlayStation 3 and PlayStation Vita have multicore CPUs and dedicate one core to DRM, and the Wii has an extra CPU (nicknamed "starlet") on the northbridge, again devoted to DRM.
If I understand correctly, Moore's law should hold out for another 4 years - that is we have mapped out the technology to get to chips down to 11 nanometers - it just a matter of implementing that technology - which is no small feat. After that - what?
3d chips - by gluing chips on top of each other
3d chips with different strata
quantum bits
quantum tunneling to replace current gates
etc.
If Moore's law is to continue, some new rabbits are going to have to pulled out of hats. Maybe this?
Copper plates between chips should take care of (most) of it as well!
Interference? Yes, if you are attempting a multi-GHz design, you better take care of your impedances and groundplanes, granted... You would have to do it in any case though.
Of course Intel and 3M can come up with something slick, but just making heat-transferring glue might (or might not!) be a deal-breaking situation. I just wanted to point this /. crowd to some prior art that I happened to know about, and that is out in the open. I bet someone liked the possibility, sorry if it were not you personally! ;)
As to "titbit" -- yes, English is not my first language, but it is, indeed, tidbit... Sorry about you that you are still so fascinated with "tits" (you know, meaty appendages attached to the chests of someone of opposite sex, with "nipples" at the end!) ;) Just kidding, but I think you were wrong...
Paul B.
Your argument about TB USB sticks is right. Imagine SSD drives and portable media players that can actually hold a significant amount of your media collection.
I was promised a flying car. Where is my flying car?
I for one, welcome our Pringles overlords.
Are they talking multiple die in the same package (Multi-Chip Packages) or multiple layers of Package-on-Package? Current MCP technology already allows 5 or so layers in a 1.4mm tall chip, while for Package-on-Package, it would be more difficult in keeping w/ any size constraints, but at least testing would be less expensive. But for servers, why don't they just have an optimal 4-core processor, and then have, say 32 of them in order to get that desired result? Something tells me this is being over-engineered, and is likely to be more expensive than it needs to.
Since when does clock rate depend on the number of cores?
Last time I heard the clock rate remained the same no matter how many chips are stacked together. At best, multiple cores can achieve a higher data processing throughput but even that's highly dependant on software parallelization.
Glue?!? Everyone knows if you want it done right you use duct tape.
Having to work for a living is the root of all evil.
HAL in your pocket, doing double duty as a pocket-warmer heat-source for those long ice-skating parties. Awesome.
"Sufficiently complicated financial instruments are indistinguishable from fraud." --bmcraec