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SSD Latency, Error Rates May Spell Bleak Future
Lucas123 writes "A new study by the University of California and Microsoft shows that NAND flash memory experiences significant performance degradation as die sizes shrink in size. Over the next dozen years latency will double as the circuitry size shrinks from 25 nanometers today, to 6.5nm, the research showed. Speaking at the Usenix Conference on File and Storage Technologies in San Jose this week, Laura Grupp, a graduate student at the University of California, said tests of 45 different types of NAND flash chips from six vendors using 72nm to 25nm lithography techniques showed performance degraded across the board and error rates increased as die sizes shrunk. Triple-Level NAND performed the worst, followed by Multi-Level Cell NAND and Single-Level Cell. The researchers said MLC NAND-based SSDs won't be able to go beyond 4TB and TLC-based SSDs won't be able to scale past 16TB because of the performance degradation, so it appears the end of the road for SSDs will be 2024."
We already have the breakthrough, but it's not Flash, it's PRAM.
Perhaps it's already been found:
http://en.wikipedia.org/wiki/Phase-change_memory
PCM still has hurdles to overcome, but it's generally considered that performance increases as size decreases, the opposite of NAND.
"A week in the lab saves an hour in the library"
They all have much lower densities. The highest is PRAM at 1 Gbit with a 58 nm process, demonstrated by Samsung in February 2011. That's way too low.