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New Manufacturing Technology Enables Vertical 3D Transistors
MrSeb writes "Applied Materials has taken the wraps off a new etching system meant to turn vertically stacked, three-dimensional transistors from lab experiments into commercial reality. The new Centura Avatar solves multiple problems facing manufacturers who are interested in 3D NAND but find their current equipment not up to the task of actually building it. According to the folks at Applied Materials, trying to build 3D NAND structures in real life would be like trying to dig a one-kilometer-deep, three-kilometer-long trench with walls exactly three meters apart, through interleaved rock strata — and that's before we discuss gate trenches or the staircases. While this machine specifically targets 3D NAND today, a number of the challenges to scaling flash memory apply to scaling CPU logic as well. As for when 3D chips will be available for commercial purchase, Applied Materials was vague on that point, but personally I would expect to see companies adopting the new etch equipment in the next few years."
"would be like trying to dig a one-kilometer-deep, three-kilometer-long trench with walls exactly three meters apart, through interleaved rock strata..."
No problem dudes, let me fire up Minecraft and I'll show you how its done!
There's two semantic goofs in this submission, one in the title and the other in the first sentence, and neither was noticed or corrected by Soulskill. The phrase "vertical 3D transistors" is misleading, since a literal interpretation doesn't describe z-axis stacking and instead describes objects whose most significant dimension is oriented vertically; it would be more accurate to write "stacked 3D transistors". In the first sentence, the adjective phrase "vertically stacked" is certainly a pleonasm if there ever was one; the definition of "stacked" already describes a z-axis or "vertical" state. The use of the word "vertical" in both of those instances is ineffective semantics.
This technology bears about the same resemblance to what Intel is doing as anaglyph 3D does to a hologram. Intel basically just stuck a 3rd gate on top of two others, stacking normal planar transistors. It's "3D" in the technical sense, but only barely. This new(ish) technology takes essentially a single block and molds it into arbitrarily many levels of transistors, so you can have a stack of dozens or hundreds deep. Much more difficult, and potentially far more rewarding.
"None can love freedom heartily, but good men; the rest love not freedom, but license." --John Milton
They aren't talking about non planar FETs ... their 3D NAND requires a far higher anisotropy (the whole 1 km deep 3 m wide bit).
And potentially far more difficult to get the heat out of.
I don't believe this is actually the *first* fab process using vertical structures (having actually RTFA). I worked at Texas Instruments in the mid-80's and most of the ALS (Advanced Low power Schottky) devices were of vertical well construction (as opposed to planar process or lateral junction bipolar construction). Looks like the sizes are a lot smaller, and the ratio of depth to width is a lot higher (a lot more junctions stacked in one well).
Chaos maximizes locally around me.
Five years are barely enough to get a small modification of a process from a research fab to a real one, if it works flawlessly. A couple more years are typical for technologies that don't work flawlessly at the first try. This process needs an antire new fab, with much more layers than normaly available, and their special etching tech. I wouldn't expect it to get mainstream soon.
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Yeah, I'm not sure what they plan on doing about that. Seems like it could be a major issue. They might not even have a solution to that yet, although TFA seems to be thinking this is going to be used for Flash memory, rather than CPU transistors, which makes heat considerably less of an issue.
NAND memory, and memory in general, is generally first in adopting new process technologies. It's far easier to make (relatively simple) memory circuits (generally consisting of a tiny number of transistors) than it is to make (relatively complex) logic circuits (consisting of orders of magnitude more transistors).
You have to understand that inside one of these "drives" is really a computer with a CPU running embedded software, I/O controllers talking to the SATA host bus, large RAM for buffering data, and a lower level flash interface to manipulate the actual flash storage. The device is then implementing a kind of filesystem on top of the raw flash, keeping track of free/erased flash blocks, wear levels, and the logical mapping to SATA block addresses.
The entire contents disappearing is not due to flash memory losing all its state at once. It is due to buggy firmware on these "drives" crapping itself and corrupting its own filesystem metadata. This is likely due to it not doing safe journaling, e.g. it performs unsafe flash write sequences that leave flash in an unexpected state if they are interrupted due to power loss or firmware bugs/resets. This is a bit like our old filesystems before they did journaled metadata for crash recovery.
I wish manufacturers would expose the flash storage and allow the OS to manage this layer, but they're too busy profiting from the illusion of firmware as just another part of the hardware. Everything seems to be trending towards more elaborate embedded software that we cannot review or maintain separately from the devices containing it, forcing artificial lifetime limits on the products.