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Samsung Develops World's Fastest Embedded Memory With eMMC 5.0 Support
hypnosec writes "Samsung has announced the world's fastest NAND memory that supports the eMMC 5.0 standard. The new memory chips are based on 10nm class NAND flash technology and feature an interface speed of 400MB/s. Further, the 32GB and 64GB densities have a random read and write speed of 7,000 IOPS (inputs/outputs per second) while the sequential read and write speeds stand at 250MB/s and 90MB/s respectively. The chips will provide for better multitasking, HD video recording, gaming and browsing."
And how many write cycles? HOW MANY CYCLES?
Well, let's say this Twinkie represents the normal number of I/O operations per second in the mobile arena. Based on this article's sample, it would be a Twinkie... thirty-five feet long, weighing approximately six hundred pounds.
I agree with most of your examples, but I can think of a situation where an SSD might help with faster 3D rendering. The soft-real-time 3D renderer in a video game is often bottlenecked by the speed of loading textures into RAM. If you've ever seen the blurfest that is the start of an Unreal Engine 3 level before the textures pop into focus, you know what I'm talking about. There's a reason that PC games load faster when installed to SSD.
It won't provide for faster anything I do on my computer, because I already have faster chips in my desktop.
I'm pretty sure that you do not have faster flash chips in your desktop.
What you have is a faster array of flash chips, a combination that only exceeds the performance here when they operate in parallel.
Now imagine these 10nm chips in an array....
"His name was James Damore."
It is about 0% faster for reads than just-released products, while about -50% faster for writes and -70% faster for IOPS.
That doesnt seem to be true. Those produces use many chips to attain their (essentially they are a RAID-0 of many flash chips) , while this is a single chip.
"His name was James Damore."
Embedded memory does not mean memory for embedded applications. It means memory that is included as a part of a larger subsystem, sometimes in a multi-chip module (MCM), sometimes in a package-on-package (POP), and the 2 main reasons for it is typically real estate constraints, as well as performance. For instance, this chip is a NAND flash that could go into MCMs that include application processors or basebands in cellphones, or it could be a part of multi-memory packages, where it's combined w/ DDR3 DRAM to provide all the memory that a portable app - such as a cell phone or GPS unit - may need.
I am curious about their 'random read and write' claims - NAND flash does not do random reads or writes: it reads or writes in pages, and so an entire buffer has to be filled before one can write anything. NOR flash is what has the random read and write: one erases in sectors/blocks and programs in bits/bytes/words. Samsung happens to make both, last I checked, so it's not inconceivable that they've combined the 2, and are offering the combination in a single package. But I'd like to know whether that's the case here.