AMD Announces First ARM Processor

MojoKid writes "AMD's Andrew Feldman announced today that the company is preparing to sample its new eight-core ARM SoC (codename: Seattle). Feldman gave a keynote presentation at the fifth annual Open Compute Summit. The Open Compute Project (OCP) is Facebook's effort to decentralize and unpack the datacenter, breaking the replication of resources and low volume, high-margin parts that have traditionally been Intel's bread-and-butter. AMD is claiming that the eight ARM cores offer 2-4x the compute performance of the Opteron X1250 — which isn't terribly surprising, considering that the X1250 is a four-core chip based on the Jaguar CPU, with a relatively low clock speed of 1.1 — 1.9GHz. We still don't know the target clock speeds for the Seattle cores, but the embedded roadmaps AMD has released show the ARM embedded part actually targeting a higher level of CPU performance (and a higher TDP) than the Jaguar core itself."

Comments

Pretty low bar...

[Anonymous Coward]

OK, RISC is good and all, but they're claiming performance well below the competition at a higher cost per flop in watts. And it's going to need everything recompiled.

Seriously, WTF happened? The Opteron 2300s were very good and extremely competitive, but AMD decided to burn that to the ground for really no reason. It's not their engineering that kills them, it's their execution. I know of no other company that can piss away 5-6 years of R&D and then claim over and over that the inferior new stuff is so great. It's mind-blowing.

Re:Pretty low bar...

[Joce640k]

But much more important, what is the benefit of using ARM over x86 here?

I don't know much about servers but ARM chips are currently outselling x86 ships. It makes sense for chip manufacturers to get into the ARM market (unless you're Intel).

Re:Pretty low bar...

[dwater]

> unless you're Intel

I'm curious about the arguments for and against for Intel...

Re:Pretty low bar...

[gtall]

And the point is that this is about servers, it doesn't matter if there are more ARM chips selling....you wouldn't compare a smart phone SoC with a server chip.

I've heard arguments on both sides about server stats for ARM vs. Intel servers. Personally, I hope Intel gets kicked in the teeth, but I have yet to see a knock down argument that ARM has what it takes to beat them. There will probably be applications for both were each excels.

Making comparisons now is also somewhat pointless. What's more important are the trajectories of both architectures, and Intel could also try to pull another Itanic, only be successful this time. At that point, attempting to plot trajectories now is pointless because a new Intel architecture is an entirely different trajectory.

Re:Pretty low bar...

[fisted]

ARM chips are currently outselling x86 ships

That doesn't surprise me at all. It might be interesting to have an ARM-powered x86 ship though.

Re:Pretty low bar...

[larry bagina]

IntEl was involved with ARM at the turn of the century -- StrongARM/XScale. They acquired it from DEC (as part of a patent settlement) in 1998 and eventually sold it off to Marvell in 2006.

Re:Pretty low bar...

[fatphil]

Well, they enterred it in 1997, and then left it? Maybe the divorce was painful.

Re:Pretty low bar...

[Uncle Warthog]

I know of no other company that can piss away 5-6 years of R&D and then claim over and over that the inferior new stuff is so great. It's mind-blowing.

Microsoft?

Re:Pretty low bar...

[dwater]

Yes, but I'm curious why it would make less (or more, even) sense for Intel to 'get into the ARM market' than any other chip manufacturer.

I can think of a reason of the top of my head - ie it might dilute their stance/marketing message that 'IA is best' or something like that, but I'm not sure if that is really true. In fact, I can imagine Intel saying, 'well, this isn't the first time we've made ARM' and that making people say, 'oh, right...ok then...nothing to see here'.

I'm just curious what other reasons the poster was thinking about...

Despite it's name

[dbIII]

Jaguar is for tablets and seems to be designed for price point and not speed. That's why they are comparing it with the ARM stuff and not using an Opteron 6386 as a comparison.

Re:Despite it's name

[Anonymous Coward]

2 * 10Gb ethernet
8 * SATA 3
128GB DDR3 RAM
great for a storage box

Re:Despite it's name

[hairyfeet]

Which is why I don't get this chip. After all they have the Jaguar for ULV applications, Opteron for when you need more horsepower, what good are these ARM units?

And I'm sorry ARM fans but as we keep seeing ARM just doesn't scale, you bump up the IPC and you blow the power budget, which is why I've been saying for awhile that days of "ARM Mania" will be quickly coming to an end. Folks want their handhelds to perform like an HTPC in their pocket and that means high instructions per second which ARM can't do without blowing through the power. This is why Nvidia is up to 5 cores, Samsung to 6, because ARM just doesn't scale. Its gonna be easier for AMD and Intel to cut X86 down with jaguar and Atom than it is to get ARM to scale.

So I just don't get what the market for this is exactly. Most server code is X86 anyway, be it wintel or Linux, so you are talking about some serious expense porting it over and with jaguar on the low end and Opteron on the high? Well i just don't see a huge market for ARM servers, am I missing something?

Re:Despite it's name

[Anonymous Coward]

Nonsense.

Most serve code can just be recompiled and it just works. Even that is not required it are are running a Linux distro.

That's before we think that a lot of server code is Java, PHP, Python, Ruby, JavaScript etc that does not even need recompiling.

I can't speak for the power budget on servers but clearly someone thinks there is a gain there.

Besides, some competition in that space cannot be a bad thing can it?

     

Re:Despite it's name

[MrEricSir]

Jaguar is for tablets and seems to be designed for price point and not speed. That's why they are comparing it with the ARM stuff and not using an Opteron 6386 as a comparison.

The question is whether Jaguar itself is really 64-bit, or if it's just the graphics processor that's 64-bit and the rest is 32-bit.

Re:Despite it's name

[Anonymous Coward]

These things seem almost purpose-built for memcached servers and... well, can't think of much else. And for a memcached box, all the profit is going to the DRAM vendors. Saw somewhere else that "AMD will take a loss on every chip, but make up for it in volume..." That sounds about right for their business plan, but can they even execute on that...? Will be an interesting year for them, I suppose.

Re:Despite it's name

[Billly Gates]

Microsoft supports Windows, IIS, SQL Server, and Exchange on ARM. Linux and its FOSS supports ARM as well. I believe RHES has an openJDK for java apps to run on ARM servers too.

Besides a few niche apps I really do not see the application compatibility problem.

It is not like these are used to run win32 desktop apps.

Re:Despite it's name

[tibman]

You would have to go way out of your way to get x86 binaries on an arm box. Your package manager certainly won't be giving you pre-built packages for the wrong architecture.

Re:Despite it's name

[dbIII]

No, you'd probably use something already built for ARM like apache and a PHP (or something better) interpreter.
We've gone full circle back to the early PC days of interpreted instead of compiled code so that leaves a space for these things.

Re:Despite it's name

[bzipitidoo]

I agree. Recompiling is not a big deal. C/C++ is standardized. The heavy lifting is the creation of standard libraries, and any sensible chip and system vendor will help do that because it's absolutely necessary. This is not the same thing as porting from an Oracle database to MariaDB or some other DB. That's a big job because every database has their own unique set of extensions to SQL.

x86 never was a good architecture. It was crap when it was created back in the 1970s, crap even when compared to other CISC architectures of that era, and despite tremendous improvement, it's still crap today. Motorola's 68000 series was superior. Intel went with a load/store design for the integer math, which is okay, but then for no good reason whatsoever they didn't stay consistent for the floating point math, opting for a horrible stack based approach. The reason the true underlying architecture of a modern x86 CPU is RISC is that RISC is just that much better. Yes, so much better that even after allowing for the overhead in translating from x86 to RISC instructions, it is still faster than a CPU that executes x86 operations natively. They've done an amazing job of working around and amending the shortcomings of the x86 design, but it would be better to ditch the legacy cruft and make a fresh start. I mean, the instruction set has specialized instructions for handling packed decimal! And then there's the near worthless string search REPNE CMPSB family of instructions. The Boyer-Moore string search algorithm is much faster, and dates back to 1977. Another sad thing is that for some CPUs, the built in DIV instruction was so slow that sometimes it was faster to do integer division with shifts and subtracts. That's a serious knock on Intel that they did such a poor job of implementing DIV. A long time criticism of the x86 architecture has been that it has too few registers, and what it does have is much too specialized. Like, only AX and DX can be used for integer multiplication and division. And BX is for indexing, and CX is for looping (B is for base and C is for count you know-- it's like the designers took their inspiration from Sesame Street's Cookie Monster and the Count!) This forces a lot of juggling to move data in and out of the few registers that can do the desired operation. This particular problem has been much alleviated by the addition of more registers and shadow registers, but that doesn't address the numerous other problems. Yet another feature that is obsolete is the CALL and RET and of course the PUSH and POP instructions, because once again they used a stack. Standard thinking 40 years ago, but today, we know that more flexibility is better, and calls and returns can be achieved with a JMP instruction that stores a return address at a location determined through some indirection, rather than using a specialized CALL and RET instruction that pigs out on a precious register to hold and update a stack pointer for a call stack, and which is a pain to work around to implement things like tail end recursion. Finally, the support for task switching, virtual memory, and concurrency was lacking. Their so-called segmented memory architecture was terrible. The first attempt at OS level instructions, in the 80286, was so badly done that hardly anyone tried to use it. The 80386 was much better, but still lacked an atomic instruction for handling semaphores. Wasn't until the 80486 that they finally got it good enough to support a real OS. That's a big reason why PCs had such a poor reputation compared to Big Iron, and were often dismissed as toys.

That's not to say that ARM and other architectures don't have issues. But the x86-- it's like they were trying for the worst possible design they could think of.

Re:Despite it's name

[Osgeld]

its been scaling since the mid 1980's and a hell of a lot more gracefully than any other cpu ever made to date, and btw even windows NT 4.0 supported arm

Re:Despite it's name

[LordLimecat]

Its not x86 today, which kind of makes me think you have no idea what youre talking about.

opting for a horrible stack based approach.

Im not one to argue architectural advantages, but id point out that both of the top two cpu manufacturers chose the same instruction set. Noone else has been able to catch the pair of them in about a decade.

Re:Despite it's name

[gmhowell]

Where you even came up with an idea like that is beyond me.

Obviously. BTW, isn't tonight a school night, kid?

Re:Despite it's name

[qpqp]

I'm sure the point was that most packages are also available as binaries for ARM.

Re:Despite it's name

[afidel]

Most business apps are written in java (as understood by one or two supported java server engines, probably not the ones available on ARM unless one of those happens to be Apache Tomcat). Seriously, most of the time even upgrading the java server to a newer subrelease will break things for any non-trivial application which is why you have very specific requirements in the support matrix.

Re:Despite it's name

[afidel]

Microsoft supports Windows (kinda), on ARM

FTFY, MS only supports a limited set of the Windows 8 client piece on ARM (specifically Modern UI based apps)

Re:Despite it's name

[ChunderDownunder]

tl;dr

Something about Kermit - I think that was a networking protocol popular in the 80s.

Re:Despite it's name

[jones_supa]

A "storage box" should not need more than 128 megabytes of RAM.

Re:Despite it's name

[ChunderDownunder]

Who cares about the client API? - We're talking about a server, which depending on the quality of Microsoft's remote admin tools, should run entirely headless. (One would hope you don't *still* need to Remote Desktop into a server in 2014 to change a trivial setting)

Even if Windows RT dies a miserable death in tablet-land, all the necessary plumbing to run SQLServer, Exchange, Active Directory etc should be present.

Re:Despite it's name

[jones_supa]

even windows NT 4.0 supported arm

Not as far as I know. Maybe you are thinking about Alpha?

Re:Despite it's name

[gbjbaanb]

Depends, if its running Windows Storage Spaces, it'll need more than the 128 GB.

Re:Despite it's name

[gbjbaanb]

its unfortunate, but sometimes the best way to drive a screw into a piece of wood is just to keep smashing at it with bigger and bigger hammers.

I guess this approach is what Intel and AMD have been doing with x86.

Re:Despite it's name

[isama]

Or anything ZFS. git it 16G minimum for caching otherwise it will work like that windows server :P

Re:Despite it's name

[fuzzyfuzzyfungus]

Write once, debug in some places, abandon all hope elsewhere...

Re:Despite it's name

[Anonymous Coward]

No of course not. Don't be silly.

But if I run a Debian setup, for example, I could just as easily use the ARM version of Debian which provides all the same packages built for ARM. I don't have to recompile anything there.

My application code, if it's in C/C++ or some other compiled language can easily be recompiled by me just like I build for x86. No problem.

All the Java, PHP stuff does not need compiling at all.

Around here we do that a lot moving code around from x86 to ARM, but so far going down scale to embedded systems not up scale to servers.

I see no reason why it should be hard. Or even much of an inconvenience at all.

Re:Despite it's name

[evilviper]

Your criticisms are probably quite apt for a 286 process. Some might be relevant to 686 processors too... But they make no sense in a world that has switched to x86-64.

The proprietary processor wars are over. Alpha and Vax are dead. PA-RISC is dead. MIPS has been relegated to the low-end. SPARC is slowly drowning. And even Itanium's days are severely numbered. Only POWER has kept pace, in fits and starts, and for all the loud press, ARM is only biting at x86's ankles.

    x86 has been shown able to not just keep pace but outclass every other architecture. Complain about CISC all you want, but the instruction complexity made it easy to keep bolting on more instructions... From MMX to SSE3 and everything in-between. The complaints about idiosyncracies are quite important to the 5 x86 ASM programmers out there, and compilier writers, and nobody else.

I wouldn't mind a future where MIPS CPUs overtake x64, but any debate about the future of processors ended when AMD skillfully managed the 64-bit transition, and they and Intel killed off all the competition. With CPU prices falling to a pittance, and no heavy computational loads found for the average person, there's no benefit to be had, even in the wildest imagination, of switching the PC world to a different architecture, painful transition or no.

Re:Despite it's name

[fuzzyfuzzyfungus]

I have no love for Android; but there is one major difference between Intel's latest and assorted ARM:

Has Intel managed to cram some impressive x86 punch into ever lower power envelopes? Yes, yes indeed. Are they the only game in town, period, if you want reasonably speedy x86s at low power? Yes, unfortunately so. And, to the degree that the threat from iPads and the like doesn't keep them in check, prices reflect that.

ARM, by contrast, lacks some punch and a lot of legacy software; but approximately a zillion vendors using undistinguished foundry processes can achieve decent results at low power. Prices reflect this.

So long as ARM remains a looming threat, Intel will price their parts such that they (by virtue of Intel's unquestioned technical prowess) are very, very, compelling. If ARM shows any signs of weakness, it'll be back to the early Pentium M days, when Intel pretended that the 'Pentium 4 Mobile' was good enough, and that a Pentium M deserved a massive price premium. Not fun, at all.

Re:Despite it's name

[fuzzyfuzzyfungus]

I suspect that the bigger problem is all those applications that are mostly just IIS/SQL Server/.NET; but have enough native binaries in assorted places to gum up the works. Not so much of an issue for fancy hyperscale web outfits that have total control over their server stack and software; but a lot of businesses depend on 3rd party software, often with a long upgrade cycle, and all it takes is a few x86 specific components to scotch the whole thing until the vendor fixes it and charges a large pile of money for the update.

Re:Despite it's name

[Kjella]

TL;DR but to paraphrase Churchill "x86 is the worst form of instruction set, except for all those other forms that have been tried". The rest are dead, Jim. The cruft has been slowly weeded out by extensions and x86-64 and compilers will avoid using poor instructions. The worst are moved to microcode and take up essentially no silicon at all, they're just there so your 8086 software will run unchanged. It's like getting your panties in a bunch over DVORAK, whether or not it's better QWERTY is close enough that the world will never change. The only reason ARM might be the next thing is legal, because there's patents tied to making a x86-compaitble processor (shouldn't they BTW start expiring soon?) while everyone can get an ARM license.

Re:Despite it's name

[angel'o'sphere]

If one thinks ARM does not scale, it would be interesting if he would point out why he thinks so.
There is no thechnical reason for ARM not to scale ...

Re:Despite it's name

[DrXym]

Most server code? Most server code is Java, Python, PHP or some other abstraction running over the hardware. Providing the runtime exists to support the abstraction it is largely irrelevant what architecture is powering it. I expect that operations that are already using Linux or some other Unix variant are well positioned to jump over. Windows based operations, not so much though Microsoft are in the cloud computing space too and this might motivate them to support ARM.

Why companies might do choose ARM really depends not on whether it is faster than Intel CPUs, but whether it is fast enough for the task at hand, and better in other regards such as power consumption, cooling, rack space etc. Google, Facebook, Amazon et al run enormous data centers running custom boot images and have teams capable of producing images for different architectures. This would seem to be the market that AMD is targeting.

Re:Despite it's name

[symbolset]

Most 10Gb Ethernet ports use a gig each just for buffers.

Re:Despite it's name

[petermgreen]

Depeneds what exactly the "storage box" is doing with the data.

If it is doing block level deduplication then ram starts to become very important since you really want to keep the deduplication tables in ram. The freenas guys reccomend 5GB of ram per terabyte of storage for ZFS deduplication.

If it's serving up the same files repeately then more ram means more chance that those files will be cached in memory rather than having to be read from relatively slow storage devices.

Re:Despite it's name

[higuita]

You are also forgetting that a x86 or a amd64 is a RISC cpu with a layer od CISC hidding the RISC. That layer takes cpu space, power and resources (both designing and working). Going to a simples CPU design saves silicon wafers, increasing the number of cpu per wafers and so increasing the profit. Also, a simpler cpu saved internal resources developing the cpu.

So AMD building ARM cpus is a way to reduce costs, increase potential profit per cpu and of course, being ready and testing the market demand for ARM CPUs

Re:Despite it's name

[TheRaven64]

That depends on how you're measuring success. If it's by fastest available CPU, by most sales, or by highest profits, then neither AMD nor Intel has been dominant since the '80s.

Re:Despite it's name

[Khyber]

You fukkin n00b. Lurk moar and learn about Atari some time.

Re:Despite it's name

[hairyfeet]

But again what EXACTLY does this give you over AMD's current offerings? Low power? nope the Jaguar has that beat. High IPC? Nope Opteron curbstomps them, so what EXACTLY are these for? After all there is a hell of a lot more X86 code for server than there is ARM and whether you are gonna run Java or not there is still gonna be bugs and headaches with switching arches, its not like every bit of code is gonna work perfectly with better efficiency than it had before.

So what am I missing here? Because other than having a checkbox that says ARM, which IMHO is a couple years too late for the party thanks to Jag and Atom, what market does this serve? Is there a market for ARM chips that suck MORE power than their Jaguar units, but less than the Opteron? The jag is actually a nice chip ya know, so I really don't see what the selling point is on these chips.

Re:Despite it's name

[edxwelch]

> Most serve code can just be recompiled and it just works.
Umm, you're hardly going to run recompiled enterprise software, without testing and certification. And what about if said software uses SIMD, or x86 assembler? That requires a rewrite.

Re:Despite it's name

[Alioth]

ARM scales fine (in another way). Sophie Wilson (one of the ARM's original developers) indeed said that ARM wouldn't be any better today than x86 in terms of power per unit of computing done. However, an advantage ARM has for parallelizable workloads is you can get more ARM cores onto a given area of silicon. Just the part of an x86 that figures out how long the next instruction is is the size of an entire ARM core, so if you want lots of cores this will count for something (for example, the Spinnaker research project at Manchester University uses absurd numbers of ARM cores).

Re:Despite it's name

[Bengie]

And harddrives should not need more than 4KB of cache.

Re:Despite it's name

[CdBee]

Windows NT was supported on ARM. As well as Alpha. I've still got a copy of it somewhere...

Re:Despite it's name

[AmiMoJo]

AMD is betting that their "APU" designs, where a GPU offloads a lot of heavy lifting from the CPU, will provide good performance and power consumption. Offloading to the GPU is actually more advanced on mobile platforms than on the desktop, so it makes sense.

Re:Despite it's name

[jones_supa]

I cannot find any evidence of Windows NT supporting ARM before Windows 8.

Re:Despite it's name

[Hal_Porter]

. I mean, the instruction set has specialized instructions for handling packed decimal! And then there's the near worthless string search REPNE CMPSB family of instructions. The Boyer-Moore string search algorithm is much faster, and dates back to 1977. Another sad thing is that for some CPUs, the built in DIV instruction was so slow that sometimes it was faster to do integer division with shifts and subtracts. That's a serious knock on Intel that they did such a poor job of implementing DIV. A long time criticism of the x86 architecture has been that it has too few registers, and what it does have is much too specialized. Like, only AX and DX can be used for integer multiplication and division. And BX is for indexing, and CX is for looping (B is for base and C is for count you know-- it's like the designers took their inspiration from Sesame Street's Cookie Monster and the Count!) This forces a lot of juggling to move data in and out of the few registers that can do the desired operation. This particular problem has been much alleviated by the addition of more registers and shadow registers, but that doesn't address the numerous other problems. Yet another feature that is obsolete is the CALL and RET and of course the PUSH and POP instructions, because once again they used a stack. Standard thinking 40 years ago.

It was standard on the 8086 (introduced in 1978). The 80368 (1985) is a general purpose register machine and can use a 0:32 flat memory mode. And modern x64 (2003) has twice as many registers and the ABI specified SSE for floating point, not 8087. Also in 64 bit mode segment bases and limits for code and data (i.e any instruction which does not have a segment override prefix) are ignored.

I.e pretty much all the things you're complaining about have been fixed and if you look at benchmarks x64 chips have been faster than their Risc competitors pretty much since x64 was introduced. Going on about segments, floating point stacks and REPNE MOVSD now is absurd.

And if you look at the way the 8086 took over from the 8080 what they did made a lot of sense. You could machine convert a CPM 8080 program to a MS DOS 8086 one and have it run fine. Meanwhile a native 8086 program had access to 1M of address space, up from 64K on 8080 and Z80. Like CPM MSDOS ran on commodity hardware which was cheaper than the big iron boxes and given most people were running things like Visicalc and Wordstar it was perfectly sufficient.

Re:Despite it's name

[TheRaven64]

The Pentium M is a good example of how Intel remains dominant. It takes about 5 years to bring a CPU to market, for any vendor. You start with an approximate transistor and power budget and an estimate of what the market will want in 5-7 years. You then start work. Hopefully, the process technology gets where you need it to be and the market does what you expect. With the Pentium 4, neither happened: they were expecting to get to 10GHz with a thermal envelope of around 60W and didn't, and the market started caring about power as laptops and dense servers became big markets. If AMD had made this mistake, it would have cost the company a huge amount. Intel's size means that they don't start just one processor design, they start ten, and gradually cull them as either it becomes clear that the market isn't doing what they expected or that their designs aren't working out. They typically have 2-3 that can be ready to go in under a year, which is how they were able to pull the Pentium-M out of a hat.

This is also why ARM's strategy has changed with ARMv8 (and, to a lesser extent, with the later ARMv7 designs). Previously, most ARM customers build chips that were an ARM design plus some customisation. This was fine for ARM's traditional markets, because they were predictable and ARM could happily succeed with a small set of designs that covered this space. With ARMv8, they intentionally delayed the launch of their own designs and worked with other manufacturers (nVidia, AMD, and so on) to produce completely in-house implementations. This makes the ARM ecosystem a lot more resilient, because individual manufacturers can aim for different niches and they can bring them all to market. And, because many of these companies make money from producing SoCs, if they don't have a CPU core that makes sense for the current market, they can license one from one of the other manufacturers and add their own things on the side.

Re:Despite it's name

[Bengie]

In which ways? Branchy code? MIPS per joule? Flops per Joule? Raw MIPS or FLOPS? Performance per core? Otherwise you're just saying something like "My semi beat your car".

Re:Despite it's name

[marcosdumay]

The more RAM, the less you use the disks, the less you wear them, and the less power you spend.

Also, you'll want services that use too many files running at the file server.

Re:Despite it's name

[marcosdumay]

I'd say something completely different.

Manufacture technologies were always the most important factor on the speed of a CPU. That meant that R&D money translated into faster chips, and all the R&D money was obviously on the market leader, first the x86 and then the amd64 architectures.

Well, manufacture is still extremely important, but it's taking bigger and bigger investiments to deliver the same gains in CPU speed. At the same time, the x86 market is shrinking, and arm64 is exploding. Expect huge changes in the future.

Re:Despite it's name

[Anonymous Coward]

Ummm, you can't just "choose" the x86 instruction set. Intel was and is very protective about the x86 ISA and AMD basically got their license through some crafty measures back in the day. Intel has long since closed that loophole. So it's not like x86 is a choice for processor designers. You can't effectively license it. Arm, on the other hand...

Re:Despite it's name

[Billly Gates]

Do you have the numbers on that? I can't find them and assumed the ARMs had better power consumption but at the cost of CPU which is fine for servers.

Unless of course these ARM ones are powerful? Jaguar is the atom competitior and recent reviews of the fastest ARMs in the latest iPhone put it in the same league as the pentiumIV and AthlonXPs of a decade ago which means it is catching up.

Re:Despite it's name

[Hal_Porter]

You are also forgetting that a x86 or a amd64 is a RISC cpu with a layer od CISC hidding the RISC. That layer takes cpu space, power and resources (both designing and working).

Look at a die shot of a x86 CPU. Most of the space is cache. The actual CPU is a small fraction. Sure on an embedded system where you care about power and die area ARM makes sense. Switching a desktop or server class machine to ARM suffers from diminishing returns because the CPU is already such a small percentage of die area.

Re:Despite it's name

[fatphil]

Total bollocks. Let's take a random CISCO (nexus 7000, the absolute first technical spec that popped out of a "10gbit phy buffer" google search):

"Port buffers:
1 MB plus 65 MB per port on ingress and 80 MB per port on egress for dedicated mode operation
1 MB per port plus 65 MB shared per 4-port group on ingress and 80 MB per 4-port group on egress in shared mode"

That's higher than several other ones I've seen, and even if you're buying a 32-port switch only to use 8 of the ports, you're still nearly an order of magnitude out. Wanna use all 32, and you're a factor of nearly 30 out.

Re:Despite it's name

[0123456]

I cannot find any evidence of Windows NT supporting ARM before Windows 8.

I suspect they're confusing it with MIPS.

Re:Despite it's name

[0123456]

That quote is not appropriate; x86 has been markedly inferior to each and every architecture displaced.

Aside from, you know, minor things like cost and performance.

Re:Despite it's name

[0123456]

Except you are forgetting about AMD and how they have a total lock on the console space for the next 5 to 7 years which should keep plenty of money flowing towards the Jaguar.

The console market is high volume on tiny margins, so that's probably a pretty small 'plenty of money'.

Re:Despite it's name

[c 0xFF]

The war is over, and x86 won. But it didn't win because it's the best, but because of economics, marketing, and the quirks of history.

It's the same story everywhere in technology, be it instruction sets, MP3 players, or video media. The winner only needs to be good enough. And x86 has been good enough, hasn't it? Not the best, of course, and by accident some things (like SSE, as you pointed out) have even been made easier.

And yet, the computing world would be better off if we could somehow break our backwards-dependency on x86 to something faster and more efficient.

Re:Despite it's name

[Rockoon]

You are also forgetting that a x86 or a amd64 is a RISC cpu with a layer od CISC hidding the RISC.

You ignorants keep saying this shit, but its not accurate at all. You have taken a small truth and inflated it into a big lie.

The small truth is that there IS a layer that converts instructions into micro-ops, that there are instructions will in fact generate 3+ micro-ops.

The big bullshit ignorant lie is that you then conclude that ALL instructions are converted into multiple micro-ops. Thats just not the case.

Its not "CISC on RISC" -- its "CISC and RISC" -- The basic technique in the inevitable conclusion regardless of which place you start. If Intel had started with RISC and was trying to increase performance, they would note that instruction bandwidth is one of their bottlenecks and would then add macro-instructions that combine common sequences of micro-instructions. Now Bobs your uncle and you have the same "translation layer" technique.

The only real rational argument is that the instruction set isnt very pretty, that its surely much uglier than it needs to be. If you were to implement all the same functionality from scratch you would be able to make it much prettier, and also in a few cases make some more optimal decisions about which instructions are shorter than others. The later isnt a real argument because pure RISC doesnt make any optimality decisions about instruction length instead choosing "all the same length"

Re:Despite it's name

[hairyfeet]

You just answered your own question, with the ARMs equaling a P4 from a decade ago whereas the jag is powerful enough to be the chip for the next gen consoles while using crazy small amounts of power, from what I read a jag sucks a couple watts more than a bobcat dual, so you are talking 20w max TDP for a quad core WITH all those GPU cores that can be used for GP-GPU or turned completely off to lower power with zero tech.

So I'm sorry to you Billy and the ARM fans but as of today the ONLY places where ARM makes sense is 1.- In mobile devices with tiny batteries, like phones, and 2.- In the embedded space where a couple of cents can be the difference between profit and loss. Everywhere else? Too little IPC for the power when compared to jag and Atom.

Re:Despite it's name

[evilviper]

R&D money translated into faster chips, and all the R&D money was obviously on the market leader, first the x86 and then the amd64 architectures.

Except x86 wasn't the most profitable, so it didn't get all the R&D money. Entire companies were built around proprietary lock-in. Without a good CPU, customers won't buy your servers, your OSes, your other software, your support contract, etc. Those proprietary architectures absolutely got lots of R&D, as multi-billion dollar businesses were depending on that competitive advantage. Companies like Oracle/Sun, IBM, and HP are still clinging to that model, and indeed, IBM's POWER processors are still competitive, usually.

Re:Despite it's name

[LordLimecat]

Once again theyre not doing anything with x86. Theyre using AMD64.

Re:Despite it's name

[LordLimecat]

Raw performance, performance-per-watt, performance-per-core.

You know of a chip that beats a haswell or even steamroller in those departments?

Re:Despite it's name

[marcosdumay]

Well, ok, margins are always bigger for loked-in products and at some time, total profits were bigger for them too, and a more open standard normally wins over more closed ones. Still, that does not apply to the x86 vs arm fight, there is a small parenthesis about arm being more open, and getting the mobile market because of it, but for servers the x86 is open enough.

Re:Despite it's name

[evilviper]

I don't disagree, EXCEPT, if AMD disappears, x86 instantly becomes 100% Intel proprietary.

Now, maybe some other company could come along and use AMD's x64 instructions, plus only the Intel x86 bits that aren't under patent or some such, some of their own, and then compilers and binaries will only need minor changes... But that's a hell of a lot of work, so I wouldn't assume it'll happen.

Re:Despite it's name

[hajile]

All criticisms of the 286 ISA are relevant today as the current x86_64 ISAs are merely extensions of that old ISA (of all the ISA in use today, only x86 and ARM have excessive cruft and of these, only ARM has been willing to step away from all of it for newer designs). People talk of continuing to bolt on new x86 instructions, but adding instructions to the decoder increase complexity at a faster than linear rate. What x86 really needs is a hard reset like ARM, but at that point, why use x86?

x86 (like javascript and many other things in technology) is proof that throwing large amounts of money at inferior technology yields results. How much power is lost on x86 instructions? If Loongson is any indicator, performance relative to native RISC (what Intel and AMD use internally) is 80%. If Intel wanted a real game, they would start using Alpha internally and add a secondary x86 to Alpha decoder and offer Alpha on the mobile end and Alpha/x86 on the mid-high end.

Itanium is gone because Intel knew from the start that the chip had no future (they had already tried this some years before with the failed i860). The long-term effect of Itanium was that it generated enough smoke and mirrors to convince the know-nothings at the top to kill all the good RISC architectures (all the R&D was pulled except for SPARC which was mis-managed by Sun Microsystems).

VAX was killed because they had Alpha. Intel killed Alpha, but every advance they have made came from the Alpha EV8 and EV9 (AVX, SMT, Quickconnect, etc), in fact, Haswell has just finally managed to go as wide in execution as EV8 designs from 2003. Alpha was the apex of computer processor design. It's telling that ShenWei was/is so power efficient despite using a reverse-engineered copy of EV56 with an updated FP (a processor designed in the mid 90's).

RMI made a MIPS64 that is a 8-core (32-thead) monster with 12MB of cache, running at 1.2GHz (specs say up to 2.0GHz). It was designed for network switches and allowed for 40Gbps of traffic per chip (10Gbps encrypted/compressed on the fly) and was rated for less than 50 watts of power, all while back on 40nm. No ARM chips are anywhere near that performance (and x86 would struggle to get that performance at 40nm and around 50 watts). MIPS is already big and Loongson seems to indicate that China is willing to throw a lot of weight behind the MIPS architecture (for example using MIPS in their upcoming 100 petaflop supercomputer scheduled for 2015).

Re:Despite it's name

[Bengie]

Or define "winning" as having a higher revenue, higher margins, more R&D, and more fab plants, when comparing any single other company to Intel.

Re:Despite it's name

[Bengie]

High volume is reliable income that can be planned around.

Re:Despite it's name

[Bengie]

Ahh, yes. Solaris "Hardware threads". Barrel processors, like hyper threading, but with 4-8 virtual threads instead of 2.

Re:Despite it's name

[evilviper]

All criticisms of the 286 ISA are relevant today as the current x86_64 ISAs are merely extensions of that old ISA

No, they aren't relevant anywhere that they've been deprecated in favor of better alternatives that are available. Ranting about a 286 not having an MMU is, of course not true of modern chips. The same goes for complaining that x86 doesn't have enough registers, when x64 certainly does.

adding instructions to the decoder increase complexity at a faster than linear rate. What x86 really needs is a hard reset like ARM

The instruction decoder is a very tiny portion of the chip in modern CPUs. It doesn't significantly affect performance or cost. It's a non-issue, that continues to get ever smaller. And that legacy support is immensely worthwhile to customers, so throwing it out would cost sales, for almost no performance or price improvement. Hell, you mentioned China's MIPS efforts in a great light, but they're going out of their way to add some x86 instructions to their MIPS chip for better binary translation. Why aren't you railing against them?

If Intel wanted a real game, they would start using Alpha internally and add a secondary x86 to Alpha decoder and offer Alpha on the mobile end and Alpha/x86 on the mid-high end.

Alpha lost. When introduced it was many times faster than x86, but despite all their R&D, the margin was closing more and more with every revision. Intel & AMD got some good stuff from Alpha, but it's not the panacea you're looking for.

RMI made a MIPS64 that is a 8-core (32-thead) monster with 12MB of cache, running at 1.2GHz (specs say up to 2.0GHz). It was designed for network switches and allowed for 40Gbps of traffic per chip (10Gbps encrypted/compressed on the fly) and was rated for less than 50 watts of power, all while back on 40nm

This is just the usual apples to oranges comparison. You could no doubt get an ASIC that'll get more throughput with even less power.

MIPS is already big and Loongson seems to indicate that China is willing to throw a lot of weight behind the MIPS architecture (for example using MIPS in their upcoming 100 petaflop supercomputer scheduled for 2015).

MIPS *was* big a decade or two ago, but they've been losing market share dramatically to ARM. MIPS has some strongholds, and there's a little talk that the parent company is going to try to turn things around, but there's no sign of progress on that front, yet. China is absolutely NOT dedicated to MIPS. They haven't put much effort into Loongson in YEARS. They claimed parity with 1GHz P4 CPUs, then sat on their hands, and did almost nothing more. They aren't willing to put in the money to make it competitive, and no private company has picked up the torch, either. MIPS remains the dirt-cheap econo-proc option.

Re:Despite it's name

[higuita]

call it whatever you want... CISC AND RISC? can be also small-CISC AND small-CISC and small-CISC AND small-CISC... but that start to translate to a plain RISC

If you would take out that translation layer and use all available micro-ops, you would call that CPU a RISC like, not a CISC like... Even if sometime you can only execute one operation, other times you CAN execute several operations, being further way from a CISC design and close to a RISC design.

anyway, that layer takes out performance, consume resources and really not needed if you change architecture... so going away saved money

Re:Despite it's name

[dbIII]

I've got a P4 (netburst Xeon but that's just a beefy P4) box still running as a ZFS fileserver for non-critical files (a convenient online archive I suppose instead of having to restore from offline media). For some jobs something like that sort of CPU power is still enough since it can almost saturate gigabit.

Re:Despite it's name

[hairyfeet]

Dude go buy an AMD Bobcat board and chunk that turkey, its just pissing through the power. the bobcat gives you dual cores at 1.7GHz (and an HD6310 if you care to do any GP-GPU tasks) and under full load it sucks less power than your P4 does idling by a good 400%+ (max on bobat is just 18w).

So unless the power is cheap to free there you'd be better off tossing the P4, netburst was a dead end that didn't give a shit about anything but raw clocks. The Atom can stomp a netburst P4 for the love of pete, those huge pipelines made its IPC just crazy low so all that power you are sucking? Just wasted energy, might as well be running a hot plate. The athlons from that period were decent, the first gen Core solo and duo were nice, but the one exception I make at the shop is netburst, that shit get relegated to the "get this cheap shit outta here" junk pile because that is what it is. you can get a Bobcat board for $80 and the increased IPC and lower power and heat will quickly pay for itself, toss the turkey man.

Re:Despite it's name

[unixisc]

Not NT. CE was. On MIPS, SuperH and ARM

Re:Despite it's name

[Rockoon]

If you would take out that translation layer and use all available micro-ops

All micro-ops ARE available in x86/AMD64. Each and every micro-op is an actual instruction of the instruction set. You don't seem to understand this, as your entire argument seems to rely on not being able to use the micro-ops directly. They are directly usable.

anyway, that layer takes out performance, consume resources and really not needed if you change architecture..

You claim that it consumes performance, but the performance winner disagrees. The advantage of RISC was higher clock rates, which remained true until the clock rate wall, at which point reducing stalls and increasing IPC became the goal, which is where CISC excels and RISC does not. The reason this is so is because RISC simply doesnt have the code density that CISC has. That 2 byte instruction on x86 that emits the 3 necessary micro-ops requires 6 or 12 bytes on RISC to perform the same operations. It doesnt take a genius to realize that one of these will have significant instruction bandwidth problems before the other as IPC increases.

Re:Despite it's name

[petteyg359]

So, take one bi-directional port and you have 146 MB, which is more than a gig(abit).

Sounds good to me ..

[dogandpants]

"breaking the replication of resources and low volume, high-margin parts that have traditionally been Intel's bread-and-butter.": Intel has served us sort-of well, only. That's one thing. I also have friends who worked there and found it unhappy. I also am personally unhappy that Intel broke Nat Semi's forward looking CPUs and that they worked on the standard salesmen's plan. ARM is a good idea, and is winning. Kudos. Good luck also to AMD.

Re:Sounds good to me ..

[viperidaenz]

If Intel thought ARM was a good idea long term, they wouldn't have sold their XScale business.

They still have a full ARM license, so there is nothing stopping making their own.

they sold it in 2006

[Chirs]

Back then the mobile space hadn't exploded yet.

Re:they sold it in 2006

[viperidaenz]

iPods had exploded, it was the year before the iPhone.

There's also absolutely nothing stopping them making ARM CPU's again. They'd also be the best in the industry, because they'd be a process node smaller than the competition.

Re:they sold it in 2006

[sjames]

I think they started exploding a little later.

Sorry, couldn't resist.

Re:ARM processing

[ne0n]

I believe you've read it wrong. Basically, AMD actually traveled back in time to develop the first ARM processor.

Not bad

[rrohbeck]

An FX-8150 has a specInt_rate of 115. I've never seen an 8350 but it should be around 130-ish, just like an Opteron 6212.

x86 IS efficient

[Crass Spektakel]

Actually x86 IS efficient for for something completely different. The architecture itself is totally unimportant as deep inside it is yet another micro code translator and doesn't differ significantly from PPC or Sparc nowadays.

x86 short instructions allow for highly efficient memory usage and for a much, much, much higher Ops per Cycle. This is just that big of a deal that ARM has created a short command version of ARM opcodes just to close in. But then this instruction set is totally incompatible and also totally ignored.

Short instructions do not matter on slow architectures like todays ARM world. These just want to safe power and therefore it fits in well that ARM also is a heavy user of slow in-order-execution.

A nice example, increasing a 64 bit register in x86 takes ONE byte and recent x86 CPUs can run this operation on different register up to 100 times PER CYCLE, all commands to be loaded in THREE to EIGHT Cycles from memory to cache. On the other hand, the same operation on ARM takes 12 bytes for a single increment operation, to load some dozend of these operations would take THOUSANDS of clock cycles.

And now you know why high end x86 is 20-50 times faster than ARM.

Re:x86 IS efficient

[luminousone11]

1 byte?, you have no idea what you are talking about. AMD64 has a prefix byte before first op code byte, so in 64bit mode no instruction is smaller then 2bytes, Also 64bit arm is a new instruction set, and it does not in any way resemble 32bit arm. The fact is 64bit ARM, looks much more CISC'y then 32bit ARM, providing access to multiple address modes for load instructions, integrating the SIMD instructions rather then using costly co-processor extensions, having lightly variable length instructions, dedicated stack register and access instructions, And in a huge break from prior arm instruction sets they drop the conditional execution instructions from the instruction set. And it manages to increase the register count from 16 to 32 to boot as well. ARM has a bright future, It is not forced to waste huge swaths of transistors on decoding stupidly scatter brained instruction encodings built from 40 years of stacking shit on top of shit.

Re:x86 IS efficient

[Anonymous Coward]

What luminousone11 said with regard to 64-bit, but even if you compare old 32-bit ARM to x86 the CISC-vs-RISC comparison doesn't go as you expect, because with triple-operands, conditional execution and data processing I frequently encounter a single ARM instruction that does the work of many multi-cycle x86 instructions, not even considering all the expensive jumps on x86 which simply get stepped over for free in ARM.

Re:x86 IS efficient

[TheRaven64]

Actually x86 IS efficient for for something completely different. The architecture itself is totally unimportant as deep inside it is yet another micro code translator and doesn't differ significantly from PPC or Sparc nowadays.

This is true, unless you care about power. The decoder in an x86 pipeline is more accurately termed a parser. The complexity of the x86 instruction set adds 1-3 pipeline stages relative to a simpler encoding. This is logic that has to be powered all of the time (except in Xeons, where they cache decoded micro-ops for tight loops and can power gate the decoder, reducing their pipeline to something more like a RISC processor, but only when running very small loops).

x86 short instructions allow for highly efficient memory usage and for a much, much, much higher Ops per Cycle.

It is more efficient than ARM. My tests with Thumb-2 found that IA32 and Thumb-2 code were about the same density, plus or minus 10%, with neither a clear winner. However, the Thumb-2 decoder is really trivial, whereas the IA32 decoder is horribly complex.

This is just that big of a deal that ARM has created a short command version of ARM opcodes just to close in. But then this instruction set is totally incompatible and also totally ignored.

Thumb-2 is now the default for any ARMv7 (Cortex-A8 and newer) compiler, because it always generates denser code than ARM mode and has no disadvantages. Everything else in your post is also wrong, but others have already added corrections to you there.

Re:x86 IS efficient

[thogard]

There is one disadvantage of the different ARM modes and that is the an arbitrary program will contain all the needed bit patters to make some useful code. This means that any reasonable large program will have enough code to support hacking techniques like Return Oriented Programming if another bug can be exploited. I would love to see some control bits that turn off the other modes.

Re:x86 IS efficient

[AcidPenguin9873]

Except that 64-bit ARM (AArch64) doesn't have Thumb. Source.So in 64-bit mode (which is what these server processors will be running in), x86-64 again has a code density advantage over AArch64.

Re:x86 IS efficient

[Hal_Porter]

Thumb-2 is a great idea but unfortunately it is not supported for 64 bit mode. 64 bit mode is AArch64 which used 32 bit fixed length instructions

http://www.arm.com/files/downl...

That being said it's not as bad as ARM32

https://groups.google.com/d/to...

So far, the LZSS routine in my code looks like this:
      THUMB2: 76 bytes
      THUMB: 76 bytes
      ARM64: 96 bytes
      ARM32: 116 bytes
(for comparison, x86 is 63 bytes)

Still it is quite a bit worse than x86. x64 incidentally is the same code size as x86

http://www.deater.net/weave/vm...

8086 58 bytes
x86_x32 66 bytes
x86_64 66 bytes
arm_thumb2 76 bytes
arm_thumb 76 bytes
m68k 88 bytes
arm64 96 bytes
z80 96 bytes
arm eabi 116 bytes

Of course this benchmark is a bit silly.

Re:x86 IS efficient

[Svartormr]

Damn, moderation mistake.

Re:x86 IS efficient

[TheRaven64]

Yes, it is a slight problem with ARM. It's also a big problem on x86 - there are a large number of ways of interpreting a two-instruction sequence depending on where you start within the first instruction. ROP (and BOP) benefit a lot from this, unfortunately. There isn't really a good solution.

Re:x86 IS efficient

[TheRaven64]

AArch64 doesn't yet have a Thumb mode. Thumb and Thumb-2 were created by examining large numbers of binaries, determining the instructions that compilers most frequently used, and then generating an instruction encoding that makes the most common instructions 16 bytes long. This is not possible with AArch64 until there is a large corpus of code to analyse and there are relatively mature compilers. In contrast, a lot of the shorter x86 instructions were ones that were used on the original 8086 / 8088, and are no longer regularly emitted by compilers. The AArch64 instruction set, however, was designed as a compiler target and so does produce quite dense code without the compression scheme. For example, it has a single instruction that allow spilling a pair of registers to the stack, which compresses function prologs and epilogs quite considerably (not compared to the ARM store-multiple and load-multiple instructions, but these add a lot of microarchitectural complication to the pipeline, whereas the store-pair and load-pair instructions are trivial to implement).

Re:x86 IS efficient

[andyhhp]

AMD64 has a prefix byte before first op code byte, so in 64bit mode no instruction is smaller then 2bytes

Nope - stack operations are just a single byte, even in 64bit mode.

Re:Why ARM?

[Gravis Zero]

power efficiency which is important in datacenters. electricity isnt free.

Re:Why ARM?

[mwvdlee]

A better instruction set.

Re:Another nail in the coffin for x86

[jones_supa]

x86 is thriving and will still be around for a very long time.

"it's not clear what GPU IP is used"

[ChunderDownunder]

I would have thought AMD would have a licensing clause as part of the sale of the Imageon (Adreno) to Qualcomm in case they ever decided to re-enter the market.

Re:ARM processing

[Chrisq]

I believe you've read it wrong. Basically, AMD actually traveled back in time to develop the first ARM processor.

No - its making a food processor for cannibals. The design brief was that you should be able to process a whole arm.

Re:Another nail in the coffin for x86

[Chrisq]

Is this another nail in the coffin for the x86 architecture? Is it realistic to expect Windows/Mac OS X for ARM in their desktop versions in the near future? (Linux is already there). Of course x86 won't suddenly disappear, but may become "legacy". Intel should start moving on the ARM front

No - ARM is still a long way off the high-end x86 chips. At the moment they largely complement each-other with some overlap in the low-mid range.

Re:Why ARM?

[Anonymous Coward]

1) cheap
2) competition
3) custom SoCs

If that is enough to work out remains to be seen.

Re:Another nail in the coffin for x86

[petermgreen]

Is it realistic to expect Windows/Mac OS X for ARM in their desktop versions in the near future?

What I find really curious is that MS did all the work needed to put a full version of windows on arm.

Then they turned it into a crippled peice of shit with artificial restricitions. No third party desktop apps, no ability to join corporate domains, third party developers pushed hard into using the windows store with it's apple-like fees (AIUI there are ways to load your own metro apps without using the store but they aren't exactly user friendly).

Re:Why ARM?

[goarilla]

Fair(er) pricing.

Competing for 0.46% of server market

[edxwelch]

The microserver market is still less than half a percent of the server market and most of that is x86, not ARM. That's probably why Calxeda went bust.

And the name: Opteron.

[drinkypoo]

They're calling it the Opteron A. Seriously, AMD? That won't be confusing, when Opteron can now mean ARM or x86_64. AMD's processor naming scheme is already confusing, and they just decided to make it more confusing. Idiots.

Re:ARM processing

[Geoffrey.landis]

It's a quip-- of course I know that ARM stands for Amalgamated Regional Militia.

Re: Until ARM gets PCI, ACPI, UEFI equivalents

[confused one]

AMD's built PCIe channels into the SOC. The dev board or reference board has PCIe risers, UEFI boot , and likely has ACPI support. Next question?

Re:ARM processing

[morgauxo]

AMD SkyNet!!!!

Re:Until ARM gets PCI, ACPI, UEFI equivalents

[confused one]

You're not looking at an Android platform, which is for the most part what you are describing. I think you'll find for these platforms there will be standard Linux support in Debian, Red Hat, etc. As I understand it, the standard Linux kernel will run on it (want to get my hands on one when they're available, not because I'm excited about ARM servers; but, because I have high performance embedded applications in mind.).

On the desktop and workstations, to get more than basic functionality, most video cards require binary blobs to function correctly in Linux. You're seeing the same thing on SoC applied to video and radio hardware. For a long time, some network adapters only worked with proprietary drivers. Driverspace will always, I suspect, have some proprietary code tied to patented features.

Bit rot on mobile phones has to do with the lack of support from hardware manufacturers after 2 to 3 years. There's no motivation for them to continue support for a 2 or 3 generation old chipset with a very limited user base. Companies just are not going to put a lot of engineering resources into legacy hardware. Speaking as someone who owns a 3 1/2 year old Samsung smartphone, I feel the pain myself; but, speaking as an engineer, I understand the reasoning.

Re:Another nail in the coffin for x86

[0123456]

So that it would compete with the iPad. I mean that crippled piece of shit(the iPad which has these same limitations) seems pretty popular among the people that want things like slate devices in the workplace.

That's because it has an Apple logo on the front.

Apple are the Lexus of the computer market, while Microsoft are the Yugo. People only buy Windows products because they want to run Windows programs, and Windows For ReTards doesn't.

Story is 6 years late. Imageon A250 first AMD/ARM

[Anonymous Coward]

Former AMD/ATI employee here, sorry the first AMD arm processor was about 5 years ago. It was an imageon A250 processor, done by the now defunct handheld division in toronto, assets sold to qualcomm.
Details here http://en.wikipedia.org/wiki/Adreno

Intel's to follow? NO?

[4wdloop]

Why would not Intel, with its fabs and process nodes, produce best ARM around?

Well it does already as Altera's Stratix 10 would use Intel's 14nm fabs.
http://newsroom.altera.com/pre...

But why not Intel itself?

Re:Intel's to follow? NO?

[Rockoon]

Intel is too busy printing money with their best fabs to be screwing around with low margin ARM parts.

Re:Why ARM?

[sjames]

Power efficiency and market competition.

Re:Why ARM?

[Bengie]

It's been a bit since I've seen the tech specs, but ARMs CPUs do not scaling well with frequency at all. Something like 900mhz is 2 watts and 1.2ghz is 10watts. ARM is highly optimized for low frequency small cache designs. As its scales up, it becomes worse than modern x64 cpus. Not to say ARM won't improve, but you can't say it's simple.

Re:Why ARM?

[Gravis Zero]

are you sure this is true about ARMv8? i saw they made significant strides in power consumption which i'm betting relates mostly to the higher frequencies.

Re:ARM processing

[Shirley Marquez]

The headline would have been more clear if they had included one more word. "AMD announces ITS first ARM processor" would have said it unambiguously.

Sometimes obvious advice is useless

[dbIII]

It's an awkward sized board so it's a matter of replacing the chassis as well, plus new disk controllers would be needed as well. A bit of power for another year or two is cheaper than that. So your advice, although obvious and thought of years ago, is useless.