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Intel and Micron Unveil 3D XPoint Memory, 1000x Speed and Endurance Over Flash

MojoKid writes: Today at a press conference in San Francisco, Intel and Micron unveiled 3D XPoint (Cross Point) memory technology, a non-volatile memory architecture they claim could change the landscape of consumer electronics and computer architectures for years to come. Intel and Micron say 3D XPoint memory is 1000 times faster than NAND, boasts 1000x the endurance of NAND, and offers 8-10 times the density of conventional memory. 3D XPoint isn't electron based, it's material based. The companies aren't diving into specifics yet surrounding the materials used in 3D XPoint, but the physics are fundamentally different than what we're used to. It's 3D stackable and its cross point connect structure allows for dense packing and individual access at the cell level from the top or bottom of a memory array. Better still, Intel alluded to 3D XPoint not being as cost-prohibitive as you might expect. Intel's Rob Crooke explained, "You could put the cost somewhere between NAND and DRAM." Products with the new memory are expected to arrive in 2016 and the joint venture is in production with wafers now.

10 of 172 comments (clear)

  1. Newegg by Snufu · · Score: 4, Informative

    As with any new 'pewter tech, I'll believe it when when it I see it on Newegg with >500 reviews, > 3.5 stars, and affordable for the average Jane/Joe.

  2. bottlenecks by peterpolle78 · · Score: 3, Informative

    At the end of the interview some guy asked a very good question. If it is really 1000 times faster you will end up with a bottleneck as even SATA 3 is nowhere fast enough. If this memory have to be used to its fullest for a normal consumer playing games for example, you need new kind of motherboards also.

    1. Re:bottlenecks by silas_moeckel · · Score: 4, Informative

      M.2 is the desktop interface for this, it supports 4 PCI 3.0 lanes at 985 MB/s per lane that is nearly 4GB/s. PCI 4.0 is not to far off and doubles that.

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    2. Re:bottlenecks by Anonymous Coward · · Score: 2, Informative

      http://www.overclock.net/t/1489684/ssd-interface-comparison-pci-express-vs-sata

      It's almost like that problem has already been thought of. Go figure.

    3. Re:bottlenecks by Forever+Wondering · · Score: 4, Informative

      SATA 3.2 (aka SATA Express) is a connector change, but is actually PCIe. PCIe is already fast enough. IIRC, Apple hooks up some SSDs directly through PCIe.

      And, PCIe can actually go "off board" via a cable (since PCIe is based on separate upstream/downstream lanes and differential line drivers). Also, PCIe 4.0 will have a transfer rate of 31.5 GB/s, yet be fully backward/forward compatible.

      Intel already has a CPU package that has two substrates wire bonded together, one for CPU and one for memory. When I saw this, I assumed it would be to accomodate HP's memrister memory. But, now, it's [obviously] been planned for this new type of memory.

      --
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  3. Re:Cost? by Anonymous Coward · · Score: 2, Informative

    I just bought 16 GiB RAM for $100, and 250 GiB nand flash for $100. This will put the price somewhere between $0.40/GiB and $6.25/GiB. So, taking an average, I'll guess that we can expect to see it priced at around $3.3/GiB. Or, about 8 times as much. :-)

  4. Re:Seems Not by Anonymous Coward · · Score: 5, Informative

    They can deny all they want - intel has been filing patents on a new type of GST PCM left and right over the last 6 years.

  5. Re:Ram replacement? by duckintheface · · Score: 3, Informative

    If we are talking MLC NAND, you are off by a factor of 10. http://www.anandtech.com/show/...

    But since the XPoint cells are individually addressable bit by bit, the comparison is probably to SLC, in which case the relevant number of P/E cycles for XPoint would be 10E8 and you are off by a factor of more than 33,000.

    --
    "He took a duck in the face at 250 knots." -- William Gibson, Pattern Recognition
  6. Re:memresistor? by Archwyrm · · Score: 3, Informative

    No, you can still soft reset. Once the kernel gets reloaded (by powering on/off and handled by the boot loader) then effectively everything in a section of your "disk" reserved for process memory ("volatile memory") goes *poof* because the new kernel isn't tracking any of it.

    Additionally with a non-volatile memory the system could be "suspended to disk" / hibernated simply by syncing all pending writes and powering off. In most cases a 1000 ms operation. Resuming would have similar performance. The machine could also resize "volatile memory" dynamically. Think growing/shrinking your /dev/mem file. You wouldn't necessarily need to have it all contiguous or represented with a single file either. Certain applications would have an expectation of contiguous memory though.

    --
    Fascism should more properly be called corporatism because it is the merger of state and corporate power. -- Mussolini
  7. PalmOS by DrYak · · Score: 5, Informative

    However, current operating systems and programming techniques aren't up to this yet. It will take a long time.

    PalmOS has been 100% RAM-only from the original Palm Pilot all the way up to Palm Thungsten III (Palm T5 with Flash, and Palm Live with a micro drive where the first to actually have a permanent main storage).
    Everything is in-RAM, everything is stored in in-RAM databases. Data saving is immediate, etc.

    (Also, although not so extreme:
    lots of embed system, usually Linux-based, only have a minimal amount of ROM as sole storage and mainly work using RAM. Though they aren't completely in-RAM oriented and still use the concept of "files" and "storage", and thus make use of ramdisk (usually tmpfs) to hold files.
    Still, that also machine which mainly count on RAM storage).

    --
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