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Intel Confirms 8th Gen Core On 14nm, Data Center First To New Nodes (anandtech.com)
Ian Cutress, writing for AnandTech: Intel's 8th Generation Core microarchitecture will remain on the 14nm node. This is an interesting development with the recent launch of Intel's 7th Generation Core products being touted as the 'optimization' behind the new 'Process-Architecture-Optimization' three-stage cadence that had replaced the old 'tick-tock' cadence. With Intel stringing out 14nm (or at least, an improved variant of 14nm as we've seen on 7th Gen) for another generation, it makes us wonder where exactly Intel can promise future performance or efficiency gains on the design unless they start implementing microarchitecture changes.
8th gen will suck as bad as 7th gen, so that means the 4th gen stuff will STILL outperform it.
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The hope is that AMD's RYZEN will be good enough to compete with Intel in performance - not just price. That will wake Intel again, since they are always relaxing when there is no competition i.e. no motive to do something more.
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Yesterday prices were leaked on AMD Ryzen. For equal peformance, the AMD parts are abot 70 percent cheaper. Intel has been goofing off for several years now. Tweaking process improvements is not innovation. Intel's Architecture is tired and needs to be rethought. I'm really surprised that Intel has been caught with their pants down.
consumer products need more pci-e lanes AMD is doing better with ryzen. 16+4+4(chip set link?) Also USB 3 may be in the cpu as well.
ryzen server / workstation may have even more pci-e lanes and will there be 1 socket systems with 32 or more pci-e lanes + chipset link + 4? that can go after the high end consumer products form intel that are a gen behind there consumer products?
Competition is quite a bit behind Intel at the moment, so no reason to move forward while they can milk this current generation. Once competition starts getting *near* 14nm.... Intel will nudge forward to keep a few steps ahead.
What's beyond 7nm though?
It's another confirmation that Moore's Law is dead. If Moore's Law were still in effect, Intel would make their new chips at smaller geometry regardless of competition because it would be cheaper to do so and that would make for fatter profits. Cost per transistor is the driver of Moore's Law. That stalled at 28nm because that was last node that could be made without resorting to multi-patterning. Scaling worked in the past because the cost to make a wafer was roughly constant. By making features smaller, you either got more chips or bigger chips for the same cost. Multi-patterning means the cost per wafer as you scale down is going up faster than the transistor count per wafer. Performance still increases but you have to have customers willing to pay more. If the cost delta is large enough, Intel my not jump to 10nm even if AMD catches up. Process performance isn't the only knob they can turn to improve performance.
Meh, if Intel would just remove most of the debugging crap almost nobody uses anymore because it was superseded by newer debugging crap(!), and dedicated the 8th gen just to bug-fixing, they'd save a lot of transistors, power, and also get a lot of good will.
Can you imagine an Intel processor where the errata sheet is not a mile long? Which you could trust your embedded products to without the fear of it being a timebomb as it happened several times already (the Atom C2000 is just the latest incarnation)? Which you could spec the features without fear they would have to be disabled because they are broken beyond any hope (TSX, Interrupt remapping on the 5520 chipset IOMMU, etc)?
Oh well. Let's hope Ryzen is good. Intel is too used to selling unfinished, improperly tested crap.
Intel needs have it's ass kicked the cutting pci-e lanes on a $400 chip that in last gen had way more no you need to go up to a $600 chip to get them back and that is on the last gen workstation / server sockets. The desktop boards have been stuck on the same pci-e lanes for years and maxing out at quad core.
AMD is going have more pci-e and more cores on the desktop boards then what intel has. With the server / workstation ones like to have even more then what the amd desktop boards have.
Hasn't the whole move from 14nm to 10nm kind of been BS because they didn't actually shrink the transistor size just the size of the interconnects between the transistors? No one has a true 10nm transistor right now or at least that's been my reading of it.
An IOMMU is quite useful to users since you can map hardware between VMs, so this is a good feature. For debugging, you do need things like being able to single step and to trap instructions, which also is important for VMs. I understand most performance related things have nothing to do with ISA and are more of a electrical engineering and physics thing
Are you sure MOORE is better?
I'm pretty sure less is Moore
When Intel struggled to get Broadwell out, their die shrink to 14nm using the architecture that they made in Haswell, you knew that they were having at least some issues. When it turned out that Haswells almost exclusively didn't properly support the new "transaction memory", to the effect that the opcodes had to be patched out, that was also kinda depressing. Skylake, their next in line, and the newest architecture update, was the last time they have even vaguely been on schedule.
Right after skylake, they announced that, instead of a die shrink to 10nm, they would add a new "optimization" step, and continue to tweak skylake instead of shrinking it. This is kabylake, which just came out in desktop and laptop properly (Xeons lag behind normally: the full suite of Skylake Xeons should be launching in a few months). They redid all their slides to show a full new arrow, giving them effectively another year to do the die shrink. Now that we are getting close to seeing what would be the next guy ("cannon lake"), who properly should be launching later this year on 10nm, we first heard that they were going to insert a "coffee lake", which would be another optimization at 14nm, for desktop, and that only laptop and low power chips would actually be on the 10m "cannon lake". And now, we find out that the first 10nm will be out for datacenter, which means an even further push back.
Summary: their older slides used to show around a summer 2016 launch for their 10nm process. Then it became a summer 2017 launch, then that became only a partial launch, and now it is looking like a spring 2018 launch. The words change, but the message is the same: "We aren't close to having 10nm be actually profitable, or possibly even all that functional".
The new plant they are building in Arizona is slated for 7nm dies, so smaller chips are coming eventually.
Looks like Moore's Law is starting to fall apart. There's what? 7nm, then Carbon transistors, then 3nm, then 1nm CPU processes left in the bag. Beyond that they can't make transistors smaller and clock speed on Carbon transistors is going to be massively heat bound. (Yes Carbon sublimates at 5000C, but your solder on your motherboard only goes to about 300-350C. Even assuming you could make Steel traces, that still only gets you to 1200C before your board traces melt let alone capacitors and other components). Interesting times.
I think they are making the chips smaller, but who really cares? (Remember: The package is far larger then the chip itself).
This can best be seen in the Xeon chips, where they use their abilities to pack even more transistors into a cpu, to include more and more cores(They are up to 26 now, I think).
They don't do it for consumer chips, because It's really difficult to sell a 8 core chip if each is even 10% slower then in the 4 core version, and there is very little consumer software to use that many cores.
No reason to upgrade when there aren't going to be significant performance increases over 4 and 6 year old machines.
Agree. I have a 14 core machine with 128GB RAM. When I quickly fire up a Debian VM to test some Ansible script or something I simply give the entire VM 64GB RAM. Huge Huge Difference. Thing boots in less than a second from a Cold start. Very useful test Rig.
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There are many tradeoffs involved in RAM design, but one basic principle is this: this bigger it is, the slower it is. This cannot be escaped. Bigger RAM means more row drivers, and/or more levels of column multplexers. Faster RAM means bigger row drivers and bigger cells. Put it all together and speed*size = heat, and RAM already needs heat sinks to be able to respond in ~20 CPU cycles.
Basically, you're never going to see big RAM fast enough to respond in a single fast CPU cycle, not even cache does that now.
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Intel should never have hired Leroy Anderson.
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hydrogen being the smallest one.
Really?
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