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Startup Offers A Chip Based On The Open Source RISC-V Architecture (computerworld.com.au)

angry tapir shared this news from Computerworld: An open-source chip project is out to break the dominance of proprietary chips offered by Intel, AMD, and ARM... A startup called SiFive is the first to make a business out of the [open source] RISC-V architecture. The company is also the first to convert the RISC-V instruction set architecture into actual silicon. The company on Thursday announced it has created two new chip designs that can be licensed... but the company will not charge royalties. That makes it attractive alternative compared to chip designs from ARM and Imagination Technologies, which charge licensing fees and royalties.
One of RISC-V's inventors co-founded the company, and he says that support is growing -- pointing out that there's already a fork of Linux for RISC-V.

73 comments

  1. You don't have to pay per unit royalties sure... by cheesybagel · · Score: 3, Informative

    But you have to pay a shitton of money to get the license. Well a shitton to a regular person anyway. If you can afford to manufacture one of these chips the license cost is probably a drop in the bucket.

  2. This might not be a bad idea by iMadeGhostzilla · · Score: 1

    The component part of the licensing, that is. I imagine if you are mass manufacturing a specific device and need mostly *some* CPU functionality for performance and battery life you can avoid paying for the parts you don't need, as opposed to buying "bulk" CPU functionality. So this might be a way to pack more processing power in the device for the same cost. The only question is how the mostly theoretical RISC-V design will hold against the well baked Intel and Arm architectures that have had so many real life special use cases baked into them over the decades.

  3. Re:You don't have to pay per unit royalties sure.. by Anonymous Coward · · Score: 2, Informative

    I see you've been courted by ARM's marketing department. They've been coming to us as well with exciting charts about how affordable ARM licensing is versus the evil expensive RISC-V. But look closely, it's bullocks.

    If all you want to do is mark Cortex-M0 chips, then ARM's DesignStart license is cheaper than hiring an engineer to put together a RISC-V. ($40K iirc). Of course ARM makes that up if you manage to ship a lot of M0 units. But if you need a wide range of ARM products, the licenses quickly get more expensive. And sadly ARM's marketing department doesn't tell you their top tier license is 20x more than their bottom end.

  4. open source? $25K for every chip feature... by Anonymous Coward · · Score: 0

    E51 Coreplex IP
    The E51 Coreplex comes with Native TileLink interface bus. We offer bridges to connect the ports to various legacy bus protocols.

    System Port
    Supports Burst transactions. Used for accessing main memory and high speed peripherals.

    TileLink to AXI4
    +$25,000
    TileLink to AHB-Lite
    +$25,000

    Peripheral Port
    Supports Atomic Memory Access. Used for accessing peripheral devices and shared memory locations.

    TileLink to APB
    +$25,000

    Front Port
    Allows other masters to write into DTIM, ITIM, System Port, and Peripheral Port address space.

    AXI4 to TileLink
    +$25,000
    AHB-Lite to TileLink
    +$25,000

    1. Re:open source? $25K for every chip feature... by OrangeTide · · Score: 3, Insightful

      Anyone can produce a RISC-V. But you can pay these guys to have a ready to synthesize solution.

      There is a free open source version, and it looks pretty good. But the free one (E310) is not going to have all of those extra bus interfaces. That makes it difficult to connect to high speed peripherals or have operate in a multiprocessor environment (especially SMP).

      Ultimately SiFive is operating a business that serves other businesses, not end users. The licensing of IP is the classic (and safest) way to operate a fabless silicon business.

      Nothing is preventing you from making your own RISC-V from scratch. Unlike something like ARM where you have to pay them fees to cover patents and trademark even if you don't use ARM's implementation. And honestly it's cheaper to license ARM's implementations than to get permission to make your own. With RISC-V the opposite is true, it's free to make your own or you can pay money to license from multiple companies, who hopefully compete with one another or differentiate in other ways.

      --
      “Common sense is not so common.” — Voltaire
    2. Re: open source? $25K for every chip feature... by Anonymous Coward · · Score: 0

      That's list price, i am pretty sure you can call, whine, and negotiate a better deal. That's how all tech companies operate when selling to other companies.

    3. Re:open source? $25K for every chip feature... by JimSadler · · Score: 1

      OK, so what can a RISK-V chip do for me than they typical Intel or AMD chip can't do? Is it faster or stronger? Does it use less power? Is there a truck load of superior software cheap or free that runs on RISC-V? I like new stuff but there has to be some advantage in using it to make it a consideration.

    4. Re:open source? $25K for every chip feature... by OrangeTide · · Score: 4, Informative

      RISC-V can be embedded into your ASIC design, which is not something you can do with an x86-64 from Intel or AMD. Not only because RISC-V tends to be smaller, but because Intel and AMD do not license their designs in such a way to allow vendors to embed the design. The other aspect or RISC-V that I think is quite interesting is that it has a wide range of configurations, allowing you to tailor an instance of the processor for your particular application.

      I expect in the near future you will see RISC-V popping up as embedded processors in cameras, TVs, smart appliances, cars, routers, and more. Places where you might have had a MIPS or ARM in the past could also be serviced by a RISC-V. And the configurations available are quite a bit more flexible than MIPS and quite a bit cheaper than ARM, making it fit a broad range of markets. In a few years you will likely be using a RISC-V in some way, even if you are still stuck on trying to force your comparisons to a narrow market of desktop PCs. (your PC's GPU will probably have one or more RISC-V cores on it to manage power and orchestrate jobs to shaders)

      Price and flexibility is the advantage here. Power is basically a solved problem, we know theoretically what the best power we can achieve for a particular computation (thanks to the laws of thermodynamics), and at a very low level that is already done by all the low power architectures, including x86. Theoretically RISC-V is as scalable as any other modern CPU architecture, and maybe someone will make a super computer out of the 64-bit variant of it some day.

      --
      “Common sense is not so common.” — Voltaire
    5. Re:open source? $25K for every chip feature... by Khyber · · Score: 0

      "RISC-V can be embedded into your ASIC design, which is not something you can do with an x86-64 from Intel or AMD."

      Boy, you must have a shitty understanding of how x86/x64 procs work now days. The entire x86 instruction set is practically stuck on a RISC-like core now days.

      See what happens when you fuck around with non-bare-metal languages? You get idiots like this that don't know the fucking architecture and make entirely wrong statements like this.

      --
      Still waiting on Serviscope_minor to wake up to fucking reality and realize that Jessica Price isn't going to fuck him.
    6. Re:open source? $25K for every chip feature... by serviscope_minor · · Score: 1

      Boy, you must have a shitty understanding of how x86/x64 procs work now days.

      He's 100% correct. Neither AMD nor Intel will license their processors for you to embed in your ASIC design. And frankly you wouldn't want them to either, because on the top end, the processors are closely tied into the fab too.

      Just because you could in theory make a small x86 core on an ASIC, doesn't mean there's a decent x86 one out there to license. Plus you still have to pay for that big instruction decoder. That's fine on a desktop or laptop chip where it's trivial compared to everything else. On an M0 sized thing it would completely dominate.

      --
      SJW n. One who posts facts.
    7. Re:open source? $25K for every chip feature... by OrangeTide · · Score: 2

      To embed an x86 into an ASIC without permission from Intel you'd have to choose one that is not patent encumbered, so a 20 year old architecture would theoretically be possible. Starting this year(2017) you could do a Pentium II or Pentium Pro, which is not too shabby really. If you took the original masks, you could start right away, but the process differences may be difficult to resolve and you'd be saddled with a bus architecture that is incompatible with the rest of your ASIC's IP. And starting from scratch in HDL would mean you'd be writing your own verification suite, not impossible but a lot of work. But RISC-V and ARM already give you much of the CPU verification that you need.

      It all boils down to money. Spend money licensing a modern RISC, or spend money recreating a 20 year old variant of x86 that carefully avoids patent infringement. One of those seems like a good business strategy, the other does not.

      (yes, I'm in the chip industry. So this isn't really just armchair hobby stuff to me)

      --
      “Common sense is not so common.” — Voltaire
    8. Re:open source? $25K for every chip feature... by Anonymous Coward · · Score: 0

      Neither AMD nor Intel will license their processors for you to embed in your ASIC design

      That's not needed since Pentium patents expired. And unless you're doing something silly like gaming, you really don't need much more power than that in the first place.

    9. Re:open source? $25K for every chip feature... by religionofpeas · · Score: 2

      That's not needed since Pentium patents expired.

      Great, now where can I get the HDL sources to embed a Pentium in my own ASIC ? Or, are you suggesting that I can just clone a Pentium myself ?

    10. Re:open source? $25K for every chip feature... by Anonymous Coward · · Score: 0

      If you took the original masks you'd have to worry about copyright as well as patents. Copyright lasts a lot longer than 20 years.

    11. Re: open source? $25K for every chip feature... by Anonymous Coward · · Score: 0

      Except they do. There is a chinese version which has intel x86 cores embedded in extra chinese ip.

    12. Re:open source? $25K for every chip feature... by Anonymous Coward · · Score: 0

      Price and flexibility is the advantage here.

      The original design from academia touted simplicity, meaning lower gate count for the same performance.

      Power is basically a solved problem, we know theoretically what the best power we can achieve for a particular computation (thanks to the laws of thermodynamics), and at a very low level that is already done by all the low power architectures, including x86.

      pfft. I really doubt we have seen the last word on power optimisation based on what is happening with radio basebands. There are CPU-based, GPU-ish, and ASIC designs. We have not yet achieved minimal power translation from code to gates for a given fabrication process.

    13. Re:open source? $25K for every chip feature... by radarskiy · · Score: 1

      "RISC-V can be embedded into your ASIC design, which is not something you can do with an x86-64 from Intel or AMD."

      Atom is definitely available as a hard IP. A quick search didn't turn up any PR on the soft IP version begin available, so I won't claim that Intel has finished it yet.

    14. Re:open source? $25K for every chip feature... by radarskiy · · Score: 1

      "If you took the original masks,"

      The last PII was on a 0.25 micron process. Have you ever done a 10x pure optical shrink and gotten *any* of polygons to print?

    15. Re:open source? $25K for every chip feature... by OrangeTide · · Score: 1

      Nope. masks are not copyright. They are under a a special 10 year law for silicon masks.

      --
      “Common sense is not so common.” — Voltaire
    16. Re:open source? $25K for every chip feature... by OrangeTide · · Score: 1

      You could do 0.25 micron process and not shrink, but that'd basically make your ASIC as expensive as it was for Intel 20 years ago.

      I'm only listing ideas, I'm not filtering out the bad ideas

      --
      “Common sense is not so common.” — Voltaire
    17. Re:open source? $25K for every chip feature... by OrangeTide · · Score: 1

      Atom is definitely available as a hard IP. A quick search didn't turn up any PR on the soft IP version begin available, so I won't claim that Intel has finished it yet.

      I wouldn't say "definitely". A lot of these guys make press releases about licensing their IP. NVIDIA made announcements a few years ago they would license GPU IP, but there is nothing on the market today. I'm going to guess the Intels and NVIDIAs of the world want huge per chip royalties. Maybe we'll see some Atoms in aerospace where the royalties are not as significant. Rad-hardened x86 could be fun.

      --
      “Common sense is not so common.” — Voltaire
    18. Re:open source? $25K for every chip feature... by radarskiy · · Score: 1

      "I'm going to guess the Intels and NVIDIAs of the world want huge per chip royalties. "

      Intel is desperate to make the Custom Foundry a thing. There are at least two sweetheart deals to get other companies to put x86 in their own SoC.

  5. This is a PR blurb by Sycraft-fu · · Score: 1

    Heavy on the "rah rah", light on the details. None of the things they are saying will matter if the chip they produce isn't good. The current chip makers out there make chips that are VERY good for their given purposes, and they have a lot of R&D going in to that. It isn't as though designing a CPU that is fast, efficient, highly capable, etc, etc is some easy feat.

    Now maybe these guys did that... but then let's see some info. What are the specs on the chip(s) and what are they designed to compete with? Let's see how it all stacks up. Talking about being "open" and low cost really doesn't matter that much, there are few markets where those would be the primary concerns. Even in things like lower end mobile devices a company will pay more to get a chip that is physically smaller and lower power consumption. So it is going to have to offer something competitive in any market it tries to go in to. What you need varies by market, the primary demands in a mobile chip are very different from a HPC chip, but regardless they have to show how they can at least compete with the existing players.

    Any time I see lots of fluff and little numbers... well that makes me think perhaps the numbers aren't all that good.

    1. Re:This is a PR blurb by Anonymous Coward · · Score: 0

      More details on their website, like https://www.sifive.com/products/coreplex-risc-v-ip/e51/.

    2. Re:This is a PR blurb by Anonymous Coward · · Score: 0

      Chip designs like ARM's Cortex series are often way too powerful for a given task. They are also very often not the primary power sink. Consider any device that takes some sensory input where the sensor is much more involved than the micro chip doing the recording. In all this use cases the performance of the micro chip is secondary and the cost is often the primary driving point. Up to the point where the silicon space is much lower than the license fees ARM wants.

      Perfect is the enemy of good and this is a field where it certainly applies. RISC-V designs don't compete with ARM in the high-end-computation or ultra-low-power range right now nor do they aim for that. That doesn't mean that there isn't a billion dollar market around ripe for more competition.

    3. Re:This is a PR blurb by Anonymous Coward · · Score: 0

      The current chip makers out there make chips that are VERY good for their given purposes, and they have a lot of R&D going in to that. It isn't as though designing a CPU that is fast, efficient, highly capable, etc, etc is some easy feat

      This is RISC, i know these days all CISC are basically layered up on top of RISC like architecture but the reason Intel and AMD chips cost so much more to make is complexity... hint: it's in the name. An actual RISC design has many advantages and many disadvantages, one of the major advantages is obviously R&D,
        it's way more simple, as a result it wont have instructions designed for specific use cases, but it was never intended to have those kind of optimisations.

    4. Re: This is a PR blurb by Anonymous Coward · · Score: 0

      R&D? Doing anything with RISC is much more expensive than doing anything with CISC, with one exception. What's the exception? ARM, because it has a lot of products, compilers, etc. And why is CISC so good? Because x86 is CISC, and it has decades of infrastructure built around it, and compilers are literally free and well tuned.

      Remember when Intel built a processors designed to be better than x86, and figured that the compiler programmers would optimize it perfectly? Turns out, you don't get twenty years of industry knowledge by waving your hands, and Itanium tanked hard.

    5. Re: This is a PR blurb by Anonymous Coward · · Score: 0

      R&D? Doing anything with RISC is much more expensive than doing anything with CISC, with one exception. What's the exception? ARM, because it has a lot of products, compilers, etc. And why is CISC so good? Because x86 is CISC, and it has decades of infrastructure built around it, and compilers are literally free and well tuned.

      It's more expensive cos legacy? seriously, that's a shitty reason...

    6. Re: This is a PR blurb by mikael · · Score: 1

      Intel processors are RISC internally, and have a micro-compiler to convert the CISC Intel instructions into the RISC equivalents. It's a small overhead, but given the superscaler architecture, high clock speed, it's not noticeable.

      It used to be the case that the 80386 instructions had the REP prefix, which would allow one instruction to be repeated up to 256 times. For some reason, they didn't extend this to the floating-point instructions and now seem to have dropped it entirely.

      --
      Vintage computer adverts: http://www.vintageadbrowser.com/computers-and-software-ads
    7. Re: This is a PR blurb by religionofpeas · · Score: 1

      It's a small overhead, but given the superscaler architecture, high clock speed, it's not noticeable.

      It's not actually an overhead, because the translation also does a bunch of stuff to optimize the code, such as:

      the REP prefix, which would allow one instruction to be repeated up to 256 times

      They don't need REP, because the instruction translator automatically unrolls loops.

  6. Re:You don't have to pay per unit royalties sure.. by Anonymous Coward · · Score: 0

    A regular person won't have a silicon fab in their basement.

  7. Re:You don't have to pay per unit royalties sure.. by sunking2 · · Score: 2

    If only there was this way to program a gate array in the field.

  8. Sample? by Anonymous Coward · · Score: 0

    So, this is on silicon already? What do I have to do to get my hands on a few samples?

  9. Why is the Intel ISA not an open standard yet? by Anonymous Coward · · Score: 0

    It's everywhere and has been around for decades. Anything else that's been around as much and as long, has become a standard and free of any patents. We need more companies putting out Intel-compatible CPUs to break up their monopoly. And discrete graphics boards, as well.

  10. Bigger issue I am still not seeing resolved: by Anonymous Coward · · Score: 1

    A Pi-like SoC offering low end desktop equivalent memory+i/o capabilities and/or a Desktop compatible chip capable of using standardized bus technologies to interface with expansion cards, peripherals, and memory busses to allow it to compete, even 'unfairly' from a performance/utility point of view, against the modern Wintel desktop PC design, perhaps opening the floodgates for other cpus/systems utilizing standardized busses and expansion cards on a variety of alternative architectures and operating systems. Homogenous architectures on the level of the entire world are an increasingly bad thing, and unless we start returning the power of choice to the people they will only continue to get worse.

    And no, none of the current alternatives ARE alternatives because they all make the same bad (for the customer/owner) design decisions which result in personal insecurity in exchange for institutional security theater. Much like transportation authorities and law enforcement have become in the US and abroad.

  11. RISC V by Anonymous Coward · · Score: 1

    I have been following the whole RISC V thing for a while now and all I can say is finally!

    This is good for security. Finally a CPU that isn't backdoored out of the box. Right now there isn't really a good alternative although there have been many attempts at producing free (as in freedom) hardware.

    https://www.crowdsupply.com/raptor-computing-systems/talos-secure-workstation
    https://puri.sm/ (not completely free)

  12. RISC-V? by Anonymous Coward · · Score: 0

    Sounds a little RISC-E. Yep, I went there.

    1. Re:RISC-V? by Anonymous Coward · · Score: 0

      or for the Canadians RISC-EH?

  13. IOT only by Anonymous Coward · · Score: 0

    This may be useful for IOT sensors. But beyond that, you need 64 bit. You can't make a modern smartphone without a 64 bit CPU. You can't even make an Amazon Echo-like device without 64 bit.

    I will wait for the 64 bit version which is arriving "soon".

    1. Re:IOT only by Anonymous Coward · · Score: 0

      Bullshit.

    2. Re:IOT only by dreamchaser · · Score: 2

      Did you even look at their website or the product manual? It's already designed around a 64 bit core.

      https://www.sifive.com/documentation/coreplex/e51-coreplex-manual/

    3. Re:IOT only by ledow · · Score: 1

      You mean the Amazon Echo:

      https://en.wikipedia.org/wiki/...

      https://www.ifixit.com/Teardow...

      With 256Mb RAM, 4Gb NAND, and a 32-bit chip:

      http://www.ti.com/product/DM37...

      that's based on an ARM Cortex-A8:

      https://en.wikipedia.org/wiki/...

      Which is a 32-bit CPU?

      Yeah. You're a twat, who thinks that the bigger the number the better and you "can't possibly" do stuff with anything else.

      I mean, seriously, did you even spend two fucking seconds thinking about it, given that one Google search and the first couple of Wikipedia articles show you how much rubbish you're talking?

  14. Re: You don't have to pay per unit royalties sure. by WarJolt · · Score: 1

    That MUST be a good solution. You know that spending a lot of money on an FPGA makes the best products.

  15. RISC vs CISC by Anonymous Coward · · Score: 0

    There's a reason CISC won out in the big arena. These folk are on acid.

    1. Re:RISC vs CISC by WorBlux · · Score: 1

      Because they translate internally to RISC, and then leverage superscaler out of order pipelines. On the silicon RISC won. On the machine code side, CISC gives your compiler a bit of wiggle room in not needing to know the micro-optimizations for every variation of the silicon.

    2. Re:RISC vs CISC by willy_me · · Score: 2

      Both CISC and RISC translate to an internal CPU microcode. The difference is that the RISC translation is generally much simpler requiring a smaller portion of the CPU die. But as CPUs get larger, this difference becomes less relevant when looking at the overall CPU.

      There are no real advantages to CISC. One used to be able to argue that the required instructions are more compact but ARM CPUs demonstrated how a similar effect can be accomplished with their Thumb2 instructions. But there are also no longer any real disadvantages to CISC either - at least with reference to larger PC class CPUs.

      So it comes down to backwards compatibility with existing software - the real reason why most of our desktops are currently powered by a CISC architecture.

    3. Re:RISC vs CISC by Billly+Gates · · Score: 1

      There is a benefit. Compatibility. Not even Intel who tried the impossible to kill the x86 with HP failed when AMD made 64 bit standard. Funny pentium IV's mysteriously started being 64 bit compabile. Hmm my hunch is Intel disabled it to make Itanium look better and with a simple patch enabled the other bits

      But x86 today translates the instructions to risc internally anyway. But powermacs used more ram in the 1990s than WIndows because risc cpus created more code to bloat it in disk and ram

    4. Re:RISC vs CISC by willy_me · · Score: 1

      But x86 today translates the instructions to risc internally anyway.

      No, internally there is no CISC or RISC - just multiple stages of the CPU. The internal microcode is derived from the input CISC/RISC instruction and controls the hardware along the various stages of the pipeline. To suggest the CPU is RISC internally is erroneous because internally it is neither RISC or CISC.

      But powermacs used more ram in the 1990s than WIndows because risc cpus created more code to bloat it in disk and ram

      A bit of a stretch considering the platforms ran different operating systems. Remember that we are taking about an OS (MacOS) that never even had real virtual memory. I would suggest that compiler and coding inefficiencies had far more to due with difference in memory requirements. Far more incentive to optimize when deploying on Windows.

    5. Re:RISC vs CISC by mikael · · Score: 1

      That's was before DLL's and .SO shared object library files. Before then, every application available on the system had to be statically linked with every library that it used. X-windows/Motif applications using sockets, RPC, multi-threading would be hundreds of megabytes in size. Once it was figured out that these libraries were being duplicated, the use of dynamic linking removed the bloat.

      --
      Vintage computer adverts: http://www.vintageadbrowser.com/computers-and-software-ads
  16. Re: You don't have to pay per unit royalties sure. by Anonymous Coward · · Score: 2, Informative

    This is about security. Cost is second. If I can implement an open source RISC-V processor, don't you get that I could audit every instruction executed, as well as the means to execute those instructions? Most people blindly support a black box known as Intel or AMD to execute their instructions. There could be a dozen things undocumented hiding in that box that you never knew about, whether planted there unintentionally as bugs, or intentionally by governments and large companies.

  17. It's not the only question by dbIII · · Score: 1

    It's not the only question - there is also the question of "what can I run my existing stuff on that is better than a now very old RISC based system?".

  18. Re:You don't have to pay per unit royalties sure.. by arglebargle_xiv · · Score: 1

    Exactly. With the RISC-V you just have to fab a more or less orphan design yourself and then invent the entire support infrastructure from top to bottom as you do it. As opposed to buying a universally-supported device for $1 or so (at the performance level of the RISC-V), in units of millions if you really need that many, from any random vendor or supplier you care to name. If you're Microchip (PIC32) or Atmel (AVR32) you can afford to do your own custom architecture (and even those are somewhat niche-market things), but for anything else you need to stick to ARM.

    Look, I get that RISC-V is geek cool. It's not, and never will be, a commercially viable product, because it's competing with an entire, vast ecosystem, not just one chip sitting in isolation. Let's not pretend that it's anything other than a cool geek toy, and we can at least have an honest discussion on the topic.

  19. Re:You don't have to pay per unit royalties sure.. by religionofpeas · · Score: 1

    The point of RISC-V is not to come out with a standalone chip. The biggest market is replacement of existing cores in SoC designs. If you're already making a SoC, switching out the core is not a huge complicated ordeal.

    A perfect application would be something like the ESP8266 WiFi module https://en.wikipedia.org/wiki/...
    These modules sell for less than $2 a piece on AliExpress. I'm sure the manufacturer does not want to pay $1 in royalties for the CPU core. There are many more of those kinds of IoT devices that need reasonable processing power at minimal cost. The RISC-V would be a perfect application for those.

  20. Re:You don't have to pay per unit royalties sure.. by arglebargle_xiv · · Score: 1

    They're not paying $1 per IP core, that's why the whole module can sell for under $2. They'll be paying some insignificant percentage that's lost in the noise. It's an irrelevant amount. What they're getting in return is a complete support ecosystem that lets them build a module that sells for under $2. This can never happen with RISC-V because the licensing cost is an infinitesimal fraction of the total cost. Sure, if you state the licensing as being $200K then that sounds a lot, until you spread it across 2 billion units shipped (that's not the ESP8266, that's the Tensilica Xtensa CPU which is the bit with the ARM license). That's noise, you don't even see it in the BOM.

    Now compare that with the cost of fabbing your own RISC-V (or at least paying to have it fabbed), or paying some other boutique place who's getting it fabbed. This can never, ever compete with existing devices because it's not competing with the hundredth-of-a-cent licensing costs per ARM core shipped, it's competing with tens of billions invested in making ARM devices as cheaply as possible.

  21. The problems usually don't lie in the CPU cores... by Casandro · · Score: 1

    ... CPU cores typically are publically described in minute detail. After all people need to directly write software for those...

    Today the problem lies in proprietary hardware. Hardware for which you cannot write a decent driver as there is no public documentation available. That's the problem with modern SoCs, and that's why the mobile operation system scene is so dead right now.

  22. Re: You don't have to pay per unit royalties sure. by religionofpeas · · Score: 1

    Cost is second. If I can implement an open source RISC-V processor, don't you get that I could audit every instruction executed, as well as the means to execute those instructions?

    If cost is second, you can also get an source license for an ARM core, and audit every instruction.

  23. Re:You don't have to pay per unit royalties sure.. by religionofpeas · · Score: 2

    the Tensilica Xtensa CPU which is the bit with the ARM license

    The Tensilica CPU is not an ARM. It is presumably cheaper, but not free, and which burdens them with the cost of learning a relatively unknown CPU architecture. If you're going to take that cost, you might as well drop in a RISC-V core, and pay nothing, plus you get to benefit from the growing open source infrastructure around it.

    Now compare that with the cost of fabbing your own RISC-V

    The company that makes the ESP8266 is already fabbing the SoC, so there is no extra cost for the RISC-V.

    it's not competing with the hundredth-of-a-cent licensing costs per ARM core shipped,

    ARM charges 1.2% of the chip price for a Cortex. So, for a $1 chip, that's 1.2 cents. May not seem like a huge deal to you, but apparently it mattered enough not to get an ARM.

  24. Re:You don't have to pay per unit royalties sure.. by arglebargle_xiv · · Score: 1

    Ah, yeah, sorry, shouldn't post at 3am :-). Two more comments and then I'd better get some sleep, unless they can magic the masks and other components out of nothing, the cost of creating RISC-V stuff is going to be considerable, and the 1.2% figure is the starting point for negotiations with ARM, not a hard limit. No-one knows, or at least no-one will ever say, what prices are being charged in practice but it's well under 1.2% in many cases. Also, the reason why Tensilica didn't go ARM is because it was founded by ... what's-his-name, ex-MIPS, so they'd be unlikely to become an ARM shop. Cost may have been some factor, but the main reason would have been to do a MIPS-ng.

  25. Re:You don't have to pay per unit royalties sure.. by religionofpeas · · Score: 2

    unless they can magic the masks and other components out of nothing, the cost of creating RISC-V stuff is going to be considerable

    Not really. They are already making ASICs with their own stuff. And those ASICs already have a core of some sort. Taking out the HDL from the core, and inserting other HDL for another core, doesn't really change anything in their process. A CPU core is relatively simple piece to synthesise, all straight digital CMOS with standard library components.

    If and you're starting with a new ASIC, it's even easier to pick a free core from the beginning. And when you're doing a second ASIC based on the same core, it's almost no work at all.

  26. Intel/AMD background by knorthern+knight · · Score: 1

    > There is a benefit. Compatibility. Not even Intel who tried the impossible to kill
    > the x86 with HP failed when AMD made 64 bit standard. Funny pentium IV's
    > mysteriously started being 64 bit compabile. Hmm my hunch is Intel disabled
    > it to make Itanium look better and with a simple patch enabled the other bits.

    Yes, there was a conspiracy, but you've got it wrong.

    * The original IBM PC ran on an 8088. This was an 8086, 16-bit real mode CPU, with an 8-bit bus. 16-bit peripherals were scarce back then.

    * In the early 1980's, IBM was *THE BIG NAME* in computers, and Intel was much smaller than it is today. IBM, being IBM, demanded, and got, a "second source" written into the contracts for 8086/8088 CPUs. The biggest second source player happened to be AMD. There was also the NEC V20 CPU and Cyrix, and possibly other bit players.

    * A few years later, Intel stepped up to the 80286 and AMD followed.

    * Intel sued, claiming that the original "second source" clause did not cover the 80286. AMD fought it in court, claiming the 80286 was basically a derivative of the 8086/8088.

    * Eventually, AMD got their way. The settlement gave them the right to manufacture 80286 and other derivatives descended from the 8086/8088. Part of the settlement involved cross-licencing IP in the 8088 and derivatives.

    * Intel came out with 32-bit 80386. The "SX" version had a 16-bit bus, and the "DX" version had a 32-bit bus. AMD followed.

    * Intel came out with the 80486 and 80586 (Pentium). Again, AMD followed. Intel was pissed.

    * Now for the real conspiracy. Intel deliberately designed the 64-bit Itanium to be so totally different from the 8088-descended CPUs, that the cross-licencing agreement would not cover it. They pushed Itanium very hard, because they badly wanted a market-leading 64-bit CPU that AMD wouldn't have a cross-licence to clone.

    * In response, AMD added 64-bit extensions to their Pentium4 clone. This gave them a backwards-compatible 64-bit CPU. Meanwhile, Intel's Itanium flopped badly, being nicknamed "Itanic" in the industry. Part of the problem was that Itanium could only run 32-bit Pentium-class software via painfully slow software emulation.

    * Remember the cross-licencing agreement I've mentioned? It was a 2-way agreement. When the Itanium was obviously dead, Intel used the cross-licencing agreement to legally clone AMD's 64-bit extensions. That's how they were able to ramp up 64-bit x86_64 chips so quickly.

    --

    I'm not repeating myself
    I'm an X window user; I'm an ex-Windows user
  27. Forking the kernel is the wrong approach. by darthsilun · · Score: 1

    ...there's already a fork of Linux for RISC-V.

    Wrong approach.

    The right approach is to get involved with the upstream kernel community and get the changes they need into the kernel. Forking just means it'll always be on the sideline.

    Availability of a low cost SoC – a la RaspPi3, Pine64, or ExpressoBin – would be good too.

    1. Re:Forking the kernel is the wrong approach. by Anonymous Coward · · Score: 2, Informative

      ...there's already a fork of Linux for RISC-V.

      Wrong approach.

      The right approach is to take FreeBSD who's upstream is already mature on RISC-V and you don't have to go to look for patches.

    2. Re:Forking the kernel is the wrong approach. by sl3xd · · Score: 1

      Pretty much everything new starts as a fork, to some degree; it doesn't mean the plan is to maintain a fork - simply that the fork hasn't been merged into the kernel yet.

      Getting the code merged into the Kernel is a process, and will take time (several months at a minimum -- and probably longer, unless the code is magically perfect out of the gate). Are developers and designers supposed sit on their thumbs until then?

      As far as getting a low cost SBC computer - that's not even an apples-to-apples comparision.

      There are dozens of high performance multicore ARM designs, and millions of set-top boxes, TV's, DVD, Blu-Ray Disc, and streaming servers which use those chips. The Raspberry Pi is cheap because they selected a chip that is cheap due to economies of scale.

      AFAIK, there are only two stand-alone implementations in silicon, and they are both single-core microcontrollers. Everything else is still in the design phase, or as a 'housekeeping' co-processor in a different design (such as NVIDIA's use-case for RISCV). There is nothing approaching an economy of scale for RISCV.

      For now, a RISCV small board computer means you have the design running in an FPGA -- which is nowhere close to as cheap as a Raspberry Pi.

      --
      -- Sometimes you have to turn the lights off in order to see.
    3. Re:Forking the kernel is the wrong approach. by darthsilun · · Score: 1

      Yeahthanx. I've been using BSD since 386BSD 0.1 (and Linux/Slackware since circa 1994) but this is about forking the Linux kernel. FreeBSD isn't just not the answer, it's so far out in right field even a southpaw batter isn't going to hit there – ever.

    4. Re:Forking the kernel is the wrong approach. by darthsilun · · Score: 1

      Pretty much everything new starts as a fork, to some degree; it doesn't mean the plan is to maintain a fork - simply that the fork hasn't been merged into the kernel yet.

      Another yeahthanx. Tell us something we don't know. How long has this fork been around already? How much is already upstream?

      Getting the code merged into the Kernel is a process, and will take time (several months at a minimum -- and probably longer, unless the code is magically perfect out of the gate). Are developers and designers supposed sit on their thumbs until then?

      Yeah. Guess what part of my job is. I know exactly what's involved and how long it takes. And I've seen plenty of kernel forks that are going nowhere. Ever. Because a) getting into the mainline kernel isn't even on their radar; or b) they want to wait until they're done and think it's perfect; or c) they're too embarrassed to show their work, piecewise, to kernel devs.

      But once they've got a giant blob of code that's too big for anyone to digest, it's already too late. Or by then there's five different RISCV ports, all different, and nobody wants to do the work to make a common code base.

      So they settle for getting a fork running, and once it's running, they're so proud of it they dump the code on a web site, announce Achievement Unlocked, and they're on to whatever the next thing is.

      Sitting around on thumbs is not required. Ironically, most software devs have multiple things they can work on. And if you're diligent, there isn't that much waiting.

      I stand by my original statement: Forks of the kernel aren't newsworthy – getting it into the mainline kernel is the only thing that's interesting.

    5. Re:Forking the kernel is the wrong approach. by Anonymous Coward · · Score: 0

      I don't see the kernel debts spending any time reviewing code for an architecture from a startup with exactly zero implementations in silicon.

  28. SiFive by amoeba1911 · · Score: 1

    more like Sigh... yet another "silicon valley startup" ... is this going to be like the $400 bag squeezer?

    1. Re:SiFive by religionofpeas · · Score: 1

      is this going to be like the $400 bag squeezer?

      That was a useless product. This is an embeddable core for SoCs, which is a multi billion dollar industry.

    2. Re:SiFive by Anonymous Coward · · Score: 0

      yeah, I wouldn't knock it. It's positive and always good to see startups that actually make things and benefit the community rather than some reinvention of the wheel software that makes the wheel more square in the long run - facebook for example!

  29. Re:You don't have to pay per unit royalties sure.. by radarskiy · · Score: 1

    "unless they can magic the masks and other components out of nothing, the cost of creating RISC-V stuff is going to be considerable"

    You have to generate masks for your silicon whatever processor you use.

  30. Useless by Anonymous Coward · · Score: 0

    Admirable effort, but worthless in the end. Unlike the analagous traditional Unix or other enterprise operating systems, there's no significant cost barrier to accessing good microprocessors. Why would anyone need an alternative to AMD, MIPS or Intel ?

  31. SPARC is already open by Anonymous Coward · · Score: 0

    SPARC was opened up long time ago.
    https://en.wikipedia.org/wiki/OpenSPARC

  32. haxxx by Anonymous Coward · · Score: 0

    RISC architecture is going to change everything.