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The Secret to Tech's Next Big Breakthroughs? Stacking Chips (wsj.com)
Christopher Mims, writing for the Wall Street Journal: A funny thing is happening to the most basic building blocks of nearly all our devices. Microchips, which are usually thin and flat, are being stacked like pancakes (Editor's note: the link could be paywalled). Chip designers -- now playing with depth, not just length and width -- are discovering a variety of unexpected dividends in performance, power consumption and capabilities. Without this technology, the Apple Watch wouldn't be possible. Nor would the most advanced solid-state memory from Samsung, artificial-intelligence systems from Nvidia and Google, or Sony's crazy-fast next-gen camera. Think of this 3-D stacking as urban planning. Without it, you have sprawl -- microchips spread across circuit boards, getting farther and farther apart as more components are needed. But once you start stacking chips, you get a silicon cityscape, with everything in closer proximity.
The advantage is simple physics: When electrons have to travel long distances through copper wires, it takes more power, produces heat and reduces bandwidth. Stacked chips are more efficient, run cooler and communicate across much shorter interconnections at lightning speed, says Greg Yeric, director of future silicon technology for ARM Research, part of microchip design firm ARM.
The advantage is simple physics: When electrons have to travel long distances through copper wires, it takes more power, produces heat and reduces bandwidth. Stacked chips are more efficient, run cooler and communicate across much shorter interconnections at lightning speed, says Greg Yeric, director of future silicon technology for ARM Research, part of microchip design firm ARM.
This was thought of a long time ago and experimented with, but the real problem with it was heat. You stack silicon on top of silicon, and there's heat build-up, and heat kills. The real 'breakthrough' and 'innovation' is being down to the 10nm scale, and other lower-power options, enabling silicon to run cooler yet at faster speeds.
1st 1st
From what I remember years back, Intel was the one that started this revolution in general. They were the first to start thinking of chips in "3D" instead of "2D". The benefits were obvious, and the concept has been applied to other technologies in the years since.
https://www.intel.com/content/www/us/en/silicon-innovations/revolutionary-22nm-transistor-technology-presentation.html
Benefits: 3D circuits (with the extra potential complexity that implies), smaller chip for the same complexity (with reduced signal distance and heat generation)
Drawback: Getting heat out of the chip as only the outer layers will be next to a heat sink. Then again, we're talking 3D here... maybe they'll figure out how to weave a mesh of tiny heat pipes around the circuits.
How long until little bits of data on their Lightcycles start causing trouble?
When Fascism comes to America, it will call itself Anti-Fascism, and tell you to give up your guns.
https://en.wikipedia.org/wiki/...
Given that the brain is 3D, it's not much of a secret that you can get a more efficient layout in a 3D structure than you can in a 2D structure. It's why processor pins are on one side of the processor, as opposed to using side contacts.
A 3d-processor may be a breakthrough, but it's not a secret idea.
It's more the advances in heat mitigation, this I wager will be the new bottleneck rather that chipset size.
I don't read AC
Original BeagleBoard stacked the ARM MCU, the RAM, and the NAND flash in package on package (PoP):
https://beagleboard.org/beagleboard
In my EE grad class in 1998, we discussed chip stacking. Given the 2D manufacturing tech at the time (where chips are designed and manufactured in 2D then cut and seated in a larger housing), the biggest issue was literally how to bridge the 3rd dimension. Any imperfection in the wafer would mean an uneven seat when stacked. You have heat dissipation issues, which means a limitation in clock speed. And the simple act of aligning the layers at nm distances wasn't possible at the time. To get around this, you design a larger contact pad to allow for misalignment. The problem then was what happens when you have large plates in electric fields? That's right, capacitance, which screws up the expected voltage and creates resonance. It would revolutionize the industry, but there are a ton of technical issues to overcome.
If they solved the problem of the middle slice of the pancake having more heat than it should, 3D chip are a good solution. Plus it is easier by order of magnitude to do flat chip. So price factors in.
C. Sagan : A demon haunted world:
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visit randi.org
Isn't that the magical breakthrough that made cyberdyne so much money?
https://i.ytimg.com/vi/DGQlYCFT7d0/maxresdefault.jpg
If an experiment works, something has gone wrong.
Memory crystals, full 3-D storage. The Future. You heard it here first.
Moore's Law continues undaunted.
(Actually, circuits that turn heat into electricity are easily found in camping coolers that plug into dashboard power. The trick is to reduce them to fit as cooling layers in the chip. Some good work has already been done but the materials do not bond well with silicon. Once they realize that they can act as physical heat pipes and can figure a substance to have a connecting heat sink interact and attach to both the heat pipe material and the silicon, we will have internal chip cooling.) However, the disruptive element is not the size of the chip, nor even the power level, but the level of complexity and capability of the smaller CPU and smaller RAM and EPROM in the pipeline that will allow tiny objects to offer near-AI levels of computational autonomy and evaluation. What will they be used for will be determined later. Just as the defense department's Internet became the world's platform for commerce and communication, and smartphones became the platform for Uber and Lyft -type services, so the AI on a chip will allow new services to emerge. The future is always unexpected.
this was how the processors in the X-MP were made... two chips stacked. ran into a former Chippewa Falls worker, 2000-ish, who had a dud he's kept in a matchbox. I touched it. and it didn't file any charges....
if this is supposed to be a new economy, how come they still want my old fashioned money?
Original BeagleBoard stacked the ARM MCU, the RAM, and the NAND flash in package on package (PoP):
https://beagleboard.org/beagleboard
they just picked parts from the standard catalog and made a board
the parts they picked were POP
honestly do you think the beagleboard people have done spectacular things by finding parts in the catalog
try again when you have something actual
Your physics teacher once explained this to you by pointing out that water molecules don't need to travel from the faucet all the way through the hose for water to come out when you open the faucet. The molecules that enter the hose push the molecules that are already in there out the other end almost instantly. The drift velocity of electrons is on the order of millimeters per hour. The signal however travels as a wave at roughly 200000 kilometers per second, two thirds of the speed of light in vacuum.
Seriously, R&D on this has been ongoing since at LEAST the 80s and more likely the 70s.
One of the bigger issues is that surface area to volume really drops, so will likely have multiple heat sinks with microtubes built in between chips to carry off heat.
I prefer the "u" in honour as it seems to be missing these days.
Stacking dies is not a new concept. It isn't even new practice. Apple has been doing this with their mobile processor SoC (A8, A9, etc.) for years. (And they were hardly the first to do this.) The processor die is the bottom of the stack. The RAM die is stacked on top. This works out pretty well, since hardly any of the "pins" for the RAM need to be broken out of the package - nearly all of them go to the processor, so the finished package can actually have fewer pins overall than a standalone processor.
https://archive.fo/Af3EZ
By Christopher Mims
Nov. 19, 2017 9:00 a.m. ET
A funny thing is happening to the most basic building blocks of nearly all our devices. Microchips, which are usually thin and flat, are being stacked like pancakes.
Chip designers-now playing with depth, not just length and width-are discovering a variety of unexpected dividends in performance, power consumption and capabilities.
Without this technology, the Apple Watch wouldn't be possible. Nor would the most advanced solid-state memory from Samsung, artificial-intelligence systems from Nvidia and Google, or Sony's crazy-fast next-gen camera.
Think of this 3-D stacking as urban planning. Without it, you have sprawl-microchips spread across circuit boards, getting farther and farther apart as more components are needed. But once you start stacking chips, you get a silicon cityscape, with everything in closer proximity.
The advantage is simple physics: When electrons have to travel long distances through copper wires, it takes more power, produces heat and reduces bandwidth. Stacked chips are more efficient, run cooler and communicate across much shorter interconnections at lightning speed, says Greg Yeric, director of future silicon technology for ARM Research, part of microchip design firm ARM.
While the principles that underlie 3-D microchips are straightforward, making them is anything but. First proposed in the 1960s, the technology has sporadically appeared in high-end applications, such as military hardware, Mr. Yeric says.
But stacked-chip offerings from most major chipmakers-AMD, Intel, Apple, Samsung and Nvidia-plus smaller, specialized companies like Xilinx, have been around only five years or so, says Sinjin Dixon-Warren, an analyst at microchip research firm TechInsights. What changed? Engineers started running out of other ways to squeeze more performance out of microchips.
Stacked chips are frequently part of a "package" of other scrunched-together chips. In addition to saving space, this lets makers create many different chips-with different manufacturing processes-and then more or less literally glue them all together. The "3-D system in package" approach contrasts with the "system on a chip" approach frequently used in mobile phones, where all the different components of the phone are etched on a single piece of silicon.
One of the most advanced 3-D chip packages has powered the Apple Watch since its introduction, Mr. Dixon-Warren says. Thirty different chips are hermetically sealed inside a plastic envelope. To save space, memory is stacked on top of the logic circuit, he says. The watch couldn't be so compact without chip stacking.
But where Apple's chips are stacked only two stories high, Samsung has produced a veritable silicon high-rise. Samsung's V-NAND flash memory, used for storing data in phones, cameras and laptops, has 64 chips placed one atop the other. Samsung just announced that a future version will have 96 layers.
Nvidia's Volta microprocessors are built for artificial intelligence, with up to eight layers of high-bandwidth memory stacked onto the GPU. Shown, Nvidia chips exhibited at the Computex show in Taipei in May.
Memory is a natural application for chip-stacking technology, since it solves a problem that has long plagued chip designers: Adding more cores to anything from an iPad to a supercomputer didn't translate to hoped-for speed gains because of the communications lag between logic circuits and the memory they need to do their jobs. Sticking memory right on top of chips allows for many more short connections between the two.
That's how Nvidia's built-for-AI Volta microprocessors work, says Brian Kelleher, the company's senior vice president of hardware engineering. By stacking up to eight layers of high-bandwidth memory directly on top of the GPU, these chips are breaking records in processing efficiency.
"We are power-limited," says Mr. Kelleher, referring to the amount of
echo -e 'global _start\n _start:\n mov eax, 2\n int 80h\n jmp _start' > a.asm; nasm a.asm -f elf; ld a.o -o a;
People have been doing that for a while now.
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One simple step that could happen today is making some additional clearance under a BGA to allow capacitors to be placed under part of the package close to the power pins that seem more often than not to be centrally clustered. Or maybe, add capacitors to the underside of the package interleaved between the appropriate pins so the whole assembly can be installed in one go and not need capacitors on the flipside of the board.
Nullius in verba
to Skynet and Judgement Day.
Slashdot writers discover PoP.
Seriously, they always knew that this would be far more practical in terms of power and efficiency for silicon based circuits than putting everything on a flat die. The reason they didn't do so wasn't because they didn't know it would be any better, it was because it wasn't really feasible from a cost-gain perspective.
I asked my shop teacher in school during an section on electronics about this back in the 1980's, and he told me back then that the only reason they didn't already make 3d integrated circuits isn't because we can't really do it , but because the technology to do it properly was typically prohibitively expensive for mass production, but even then, there was no theoretical reason it couldn't be done if money was no object.
As technology improved, the cost came down, I guess. I'm not surprised.
File under 'M' for 'Manic ranting'
wasnt it one of the 386 486 586 sx dx whatever chips that you would upgrade by literally jamming another chip on top? i was little but to this day rememeber my dad lolling about it.
The GP is correct and you merely attempted to overwhelm with verbiage.
3-D construction of chip stacks is going to be wonderful, huge and will help alleviate the breakdown of Dennard Scaling. However heat dissipation is a major challenge because you cannot merely slap a cooling plate on it and you're done. Heat management is going to have to be integral to any 3-D stack.
IBM publicized that they had invented a silicon system that allowed circuits and fluid channels to co-exist, on the same wafer. You can also imagine heat pipes, or integrated heat sinks, or other schemes to draw heat out of the stack.
This is currently in large scale production as High Bandwidth Memory on AMD graphics cards, and a close relative is the package on package memories used in Raspberry Pi. Other examples include Hybrid Memory Cube. The next logical step is indeed moving more logic closer to these dies, as the controller die is overly simplistic in a HBM stack (the HMC ones are only slightly smarter). Long before that we had DIPs and coprocessors mounted in piggyback configuration.
That's a stacker. I believe earlier stuff like the BeagleBoard was as well.
In a world of the blind, the one-eyed man is king--and the two-eyed man is a heretic.
AMD was offered this in 1992 and dismissed it for all the reasons given as advantages, except as opposites: They would run hotter, they would have very poor heat dissipation, the die interconnects were not possible, et cetera.
AMD contractually released all interest in the technology in 1994.
The original document, as offered to AMD, still exists. If the author could be persuaded, it might be published.
https://www.investorvillage.com/smbd.asp?mb=2287&mn=125&pt=msg&mid=17719312
The EDRAM die on the Xeon Phi package are stacked four deep. This has been going on since at least 2005. The flash that Intel uses in SSD caches also has stacked die. How did the author not discover this during research?
I realize the WSJ hires people. And people post articles on /. to be read by even more people.
/. people have known about chip stacking for decades. Granted it has been very difficult to do previously. But so were nanometer chips back when nobody had a process that was less than a micron. No doubt WSJ will want to let their readers know the micron barrier was finally breached.
But the
WSJ and timely, accurate articles about the electronics, fab processing, computer industries are fantasies. They have never happened in my reading of them. Which is why I quit them.
Take eight 64k x 1 memory chips, stack them, solder all pins together except for the data pin, then run a wire from each data pin, and you've just made a 64k x 8 memory module. Nothing new about this.
GTFO here