To Keep Pace With Moore's Law, Chipmakers Turn to 'Chiplets' (wired.com)

As chipmakers struggle to keep up with Moore's law, they are increasingly looking for alternatives to boost computers' performance. "We're seeing Moore's law slowing," says Mark Papermaster, chief technology officer at chip designer AMD. "You're still getting more density but it costs more and takes longer. It's a fundamental change." Wired has a feature story which looks at those alternatives and the progress chipmakers have been able to make with them so far. From a report: AMD's Papermaster is part of an industry-wide effort around a new doctrine of chip design that Intel, AMD, and the Pentagon all say can help keep computers improving at the pace Moore's law has conditioned society to expect. The new approach comes with a snappy name: chiplets. You can think of them as something like high-tech Lego blocks. Instead of carving new processors from silicon as single chips, semiconductor companies assemble them from multiple smaller pieces of silicon -- known as chiplets. "I think the whole industry is going to be moving in this direction," Papermaster says. Ramune Nagisetty, a senior principal engineer at Intel, agrees. She calls it "an evolution of Moore's law."

Chip chiefs say chiplets will enable their silicon architects to ship more powerful processors more quickly. One reason is that it's quicker to mix and match modular pieces linked by short data connections than to painstakingly graft and redesign them into a single new chip. That makes it easier to serve customer demand, for example for chips customized to machine learning, says Nagisetty. New artificial-intelligence-powered services such as Google's Duplex bot that makes phone calls are enabled in part by chips specialized for running AI algorithms.

Chiplets also provide a way to minimize the challenges of building with cutting-edge transistor technology. The latest, greatest, and smallest transistors are also the trickiest and most expensive to design and manufacture with. In processors made up of chiplets, that cutting-edge technology can be reserved for the pieces of a design where the investment will most pay off. Other chiplets can be made using more reliable, established, and cheaper techniques. Smaller pieces of silicon are also inherently less prone to manufacturing defects.

Comments

Dammit

[Artem S. Tashkinov]

Our of all places on the Internet I want at least /. to admit that there has never been Moore's law - it was a mere observation": from Wikipedia, "Moore's law is the observation that the number of transistors in a dense integrated circuit doubles about every two years".

Whoever decided to call it a "law" was a moron and now we have this idiocy repeated every news story. And since it's not a law, we could simple move on and realize that physics simply doesn't allow it to exist.

Re:Dammit

[DontBeAMoran]

Especially when there's only one law: Brannigan's Law.

Re:Dammit

[enriquevagu]

You are correct. It was never a law.

Actually, it was a self-fulfilling prophecy. Since Moore's "Law" provided a reference point for the evolution of transistor density, all designers knew where they needed to get, or otherwise their competitors would surpass them.

Bicycle reinvented

[sinij]

Bicycle reinvented. These used to be called co-processors.

Re:Bicycle reinvented

[bluefoxlucid]

I've wanted a generic coprocessor architecture for a few months now. Imagine if you could stick a chip on your board and it could access the on-board video port (DVI, HDMI), a range of RAM exposed as RAM (it requests address and data), and so forth. Instead of on-CPU graphics, you have a chip that provides that. The same chip can provide things like encryption, encoding, and artificial neural networks.

These things aren't extended CPU instructions as with an FPU. They're actual separate microcomputers. An ANN chip has a completely-different architecture with memory local to the neuron's logic unit instead of in a memory bank. A GPU runs its own program against a memory space.

You don't need a huge riser and ports exposed on the card's edge. You can just plug into the board, get power and an addressing bus, and get appropriate output ports like display and DMA. You can provide multiple functions on one chip. Just make it a chip socket and make it standard.

This works for things that have to run a process on input and output, or on large bulk data. It doesn't work for things that are just extended CPU instructions, like SIMD. Transfer back and forth between processing units and the hop through the memory controller creates too much latency.

You can use a four-wire (RX,TX) LVDS memory bus, too: instead of 64 data lines and 32 addressing lines (1TB physical addressing), you can use two TX and two RX and use a packet protocol. Modern GPUs use 128-byte cache lines (seriously!). You can specify a protocol that sets memory unit size, offset, and then issues READ requests. If you want, your memory controller (on the expansion chip) could send an instruction packet {SET SIZE 512}, {READ 390625}, {READ 390626}, .... The return packet on RX would be the data. CPU's memory controller would carry out the memory read and stream the data to the RX pins.

The memory unit size is just a number of bytes. No trading off number of pins for maximum addressable RAM. There are odd reasons we use parallel buses for RAM, and it's not because parallel is faster; it's because building all of that stuff into DRAM is expensive and power-hungry. Since a coprocessor goes through a memory controller on a CPU, it's cheap there. Latency isn't as much of an issue as sheer bandwidth in this application.

Imagine it. Just pop a graphics chip on your motherboard. 12V supply that can feed 100W. If you need bigger than that, then you buy a 16-lane PCI-Express card.

Back to the future

[mspohr]

It seems that the semiconductor industry goes through these cycles periodically. Whenever they run up against limits to single chip integration, they go back to this strategy of wiring together separate chips together. Ultimately, this proves to be inefficient and once technology improves, they return to putting everything on a single chip.