Intel Reveals 10nm Sunny Cove CPU Cores That Go Deeper, Wider, and Faster (pcworld.com)

Long criticized for reusing old cores in its recent CPUs, Intel on Wednesday showed off a new 10nm Sunny Cove core that will bring faster single-threaded and multi-threaded performance along with major speed bumps from new instructions. From a report: Sunny Cove, which many believe will go into Intel's upcoming Ice Lake-U CPUs early next year, will be "deeper, wider, and smarter," said Ronak Singhal, director of Intel's Architecture Cores Group.

Singhal said the three approaches should boost the performance of Sunny Cove CPUs. By doing "deeper," Sunny Cove cores find greater opportunities for parallelism by increasing the cache sizes. "Wider" means the new cores will execute more operations in parallel. Compared to the Skylake architecture (which is also the basis of Kaby Lake and Coffee Lake chips), the chip goes from a 4-wide design to 5-wide. Intel says Sunny Cove also increases performance in specialized tasks by adding new instructions that will improve the speed of cryptography and AI and machine learning.

Comments

Have they fixed Spectre & Meltdown yet?

[Anonymous Coward]

No more CPU's will be purchased by me until these vulns are fixed.

Re:Have they fixed Spectre & Meltdown yet?

[jellomizer]

So if they don't fix it in 20 years. You will be using 20+ year old processors (that still have the problem).

So you havn't solved the problem, and you will be working with outdated equipment.

Re:Have they fixed Spectre & Meltdown yet?

[SurenEnfiajyan]

Spectre has many variants and it's almost impossible to fix all of them, it's actually the price for the performance caused by caching. Meltdown is a horrible issue and it should be shame for Intel if they not fix it in the upcoming CPU.

Re:Have they fixed Spectre & Meltdown yet?

[war4peace]

Enjoy your ancient CPU then.

Re:Have they fixed Spectre & Meltdown yet?

[SurenEnfiajyan]

Many other CPUs (including AMD and ARM) also suffer from various Spectre variants, so it's not Intel-only. Meltdown is the notorious Intel specific issue.

Re:Have they fixed Spectre & Meltdown yet?

[Megol]

Caching isn't the problem - speculative execution is. Or actually leaking speculative data into microarchitectural resources like caches. But yeah, hard to fix completely.

Re:Have they fixed Spectre & Meltdown yet?

[Megol]

X86 have nothing to do with the problem so what do you mean?

Re:Have they fixed Spectre & Meltdown yet?

[SurenEnfiajyan]

The CPU caches the data from speculative execution, this data is indirectly exposed to the application via side channel attack. Disabling speculative execution or discarding the cached data from speculative execution would greatly harm the performance, so it's unacceptable. One possible solution to this is to mark data blocks in the cache as "speculative" if they appeared in the cache from a speculative execution and when the normal code tries to access the respective data, the CPU can emulate some delay (as if it wasn't in the cache initially) and then remove "the speculative" mark. This feature could be toggled on/off by special instructions since many applications don't need to protect themselves from themselves (Spectre in user address space). But this would be useful for something like browser JS/WASM engine which execute untrusted code in their address space. This are just my ideas on how could be the security enhanced.

deeper? wider? faster?

[Anonymous Coward]

Uncut?
Geez guys - are these CPUs or porn descriptions?! I thought we were trying to get away from sexism in the tech industry!

what about more pci-e lanes?

[Joe_Dragon]

what about more pci-e lanes?

Re:what about more pci-e lanes?

[AHuxley]

Thats more money to invest in more "tech" that's not "free" on consumer level products :)

Re:what about more pci-e lanes?

[DigiShaman]

Nope. That, like ECC, will be reserved to segment that market and push power users (Workstation) to the Xeon platform. They're intentionally fucking with the market here, and I hope AMD eats their lunch over it!

As for AI - those instruction sets aren't for you. It's for enhanced analytics to profile your actions for THEIR (not yours) benifit. Call it "shadow computing" where it burns cycles on these enhanced analytics unbeknownst to you.

More pepole have seen the Loch Ness monster

[JoeyRox]

Than have seen a 10nm Intel microprocessor.

Re: More pepole have seen the Loch Ness monster

[UnknowingFool]

Yeah Intel can announce all the upcoming designs they want to announce. Will they produce sufficient quantities of chips is the main question consumers have about 10nm chips?

Re:Deeper... cache?

[TuringTest]

Just guessing: there are several levels of cache. If the lowest level is larger, it can perform more operations at this "deep" level without hitting a cache miss.

BTW I also thought about pipeline depth, but hey, that's marketing for you - unconstrained by earlier technical terms used in a different context.

They FUCK US harder for the NSA you say?

[Anonymous Coward]

Intel owes us money for the decades of lies and selling out our security to the NSA.

Fuck Intel.

CPU Cores That Go Deeper, Wider, and Faster

[xxxLCxxx]

Intel Reveals 10nm Sunny Cove CPU Cores That Go Deeper, Wider, and Faster

And with every bug mitigation it keeps getting slower, while remaining vulnerable (as the hardware is broken).
Intel does the benchmarks without mitigations. How charming.
Now you know what the bunny commercial really meant: They're fucking you over and over and over and over...

Re:CPU Cores That Go Deeper, Wider, and Faster

[xxxLCxxx]

Intel first premiered their ad campaign featuring them in a tv commercial where in a microprocessor fabrication lab the technicians are wearing suits which they use in the dust-free environment. Suddenly a technician pops in a sleek new state-of-the-art Pentium II microchip and the computers come alive with music and videos, while the 'bunnies' start breakdancing in space suits.

Why are they called bunnies? It's the name of the ad, plus Intel's new models. Thus Intel's huge ad campaign began, including 2 tv spots for the Super bowl.

I was being sarcastic. THEY are fucking us over.

Sunny Cove?

[Garabito]

No more lakes then?

What's next? Cloudy, Rainy and Foggy Cove?

Re:Sunny Cove?

[saider]

Don't forget Smokey Cove.

Re:Sunny Cove?

[Anonymous Coward]

How about islands? Lonely Island, Island of Solitude, Island of Doom, Fantasy Island. I see so many islands that fit their situation

Intel shills LIE about spectre

[Anonymous Coward]

We all know how all Intel CPUs are broken, but the why is very important.

AMD invented 64-bit for x86 chips AND invented the first true dual core x64 part. At that time AMD had a massive lead over Intel, and it's god-awful, hyper long pipeline Netburts. Tho outlets like Slashdot and Anandtech informed you, at the time, that Netburst- with its race to 10GHz- was the WINNING architecture.

Then Netburst went bust, and Intel went back to the Pentium 3, updated it with AMD's best ideas (legal due to cross patent agreement) and produced the Core 2 architecture.

But, here's the thing. Intel made the NSA and performance friendly decision to BREAK multi-threading on the CPU.

Proper on-chip multi-threading MUST be 'lock and key'. This means each thread has a unique ID, and that ID acts as a 'key' to open the 'lock' of memory resources that thread has the right to access. Intel NEVER implemented 'lock and key' but AMD always did.

So what did Intel's CHEAT achieve apart from ensuring the NSA always has low level access to your Intel CPU?

1) massively improved memory latency, for the hardware mechanism that implements the 'lock' has a real impact on access speeds.
2) massive improvements on power efficiency (the lock and key takes power for each memory access)
3) much higher clock speeds due to 1 and 2

In other words, ALL the advantages Intel seemed to have over AMD from the core 2 onwards were down to Intel using an illegal (in CS terms) broken by design CPU architecture.

Today the ONLY way to fix the Intel issue is to run ONE thread at a time on the CPU, and do a complete state flush between multi-tasking thread exchanges. The performance hit would approach 80-95%, which is why no solution uses this extreme but correct adjustment.

Next year, AMD's Zen 2 (ryzen 3) utterly wipes out Intel- and Intel will never recover. But Intel sits on a literal mountain of cash, so expect no end of PAID Intel promotion on sites like Slashdot in the continuing future.

Re:Intel shills LIE about spectre

[Lost Race]

Next year, AMD's Zen 2 (ryzen 3) utterly wipes out Intel- and Intel will never recover. But Intel sits on a literal mountain of cash, so expect ...

... Intel to buy AMD or license the Zen architecture. Or maybe just steal it.

Re:Intel shills LIE about spectre

[Shazatoga]

Jim Keller (the guy responsible for AMD64 and lead engineer for AMD's Zen architecture) started working for Intel earlier this year.

Re:Intel shills LIE about spectre

[drinkypoo]

BTW copying what Intel did to move from 16 -> 32 bits but doing it to go from 32 -> 64 bits isn't "inventing" anything.

It's too bad you can't read, or you might have looked at some of the technical documentation. They didn't copy what Intel did. When Intel went from 16 to 32 bits they replicated all the misfeatures of the instruction set, like forcing the results of an operation into specific registers, and keeping a minuscule number of registers for that matter. AMD threw all that garbage away for x86_64. When operating in 64 bit mode, it's like a completely different processor, and in fact, a relatively sane one. You don't have to all the stupid, performance-sapping tricks you have to do with the x86.

Re:Intel shills LIE about spectre

[Agripa]

1) massively improved memory latency, for the hardware mechanism that implements the 'lock' has a real impact on access speeds.
2) massive improvements on power efficiency (the lock and key takes power for each memory access)
3) much higher clock speeds due to 1 and 2

The TLB is used for every memory access so the permission check is free. Intel only acts on the permission check at instruction retirement where other faults are detected. AMD apparently uses the free permission check to prevent further speculation.

Sunny Cove:

[pak9rabid]

Bigger, Longer & Uncut.

Speed bumps?

[chthon]

Isn't their purpose to reduce speed?

Still has IME?

[Anonymous Coward]

Does it still have IME which can't be turned off? (Yes, AMD has PSP.)

Is it still subject to a wide class of speculative execution vulnerabilities?

You know, you're right but...

[Anonymous Coward]

It's the way that you say it, that makes them reject it. So with that, you're actually harming your cause.
It's like with other religious people: Be nice to them. They can't help it. They just want to keep their self-respect. So leave them a way out. (!!) So they are not idiots that could become normal. They are people who can become even better, and future awesome people.
And you'd be the one saving them, and improving their lives. Which would give us allies, and improve all our lives too.

Finally

[Artem S. Tashkinov]

I'd like to draw everyone's attention to this tidbit from the Q&A session:

Q: A lot of the CPU microarchitecture at Intel has been hamstrung by delays on process node technology. What went wrong, and what steps have been made to make sure it doesn't happen again?

This is a function of how we as a company used to think about process node technologies. It was a frame tick (limiting factor) for how the company moved forward. We've learned a lot about how this worked with 14nm. We now have to make sure that our IP is not node-locked. The ability to have portability of IP across multiple nodes is great for contingency planning. We will continue to take aggressive risks in our designs, but we also will have contingency. We need to have as much of a seamless roadmap as possible in case those contingencies are needed, and need to make sure they are executed on ASAP if needed to keep the customer expectations in line. You will see future node technologies, such as 10/7, have much more overlap than before to keep the designs fluid. Our product portfolio on 14nm could have been much better if our product designs were not node-locked to 10nm.

It's really strange it has taken them so long to come to this conclusion. As a result of their 10nm fiasco (they still avoid talking about this node openly) we're stuck with the Skylake uArch which was released in 2015. Hopefully this blunder is a thing of the past.

Re:Finally

[Targon]

Fab process improvements will not fix or change the actual CPU design, it's just the implementation. The shift from the old Pentium 3 to the Pentium 4 was a significant change to the actual CPU design. Then, Intel went back to the Pentium 3 as the basis for much of the Core design. Improvements have been made, but Intel hasn't been forced to actually come up with a fully new design in a VERY long time, so all we see have been tweaks. IPC being stagnant for years is how you see that fundamental problem. More L1, L2, and L3 cache will help feed the existing design better, but it's still the same basic design. Make the same design wider, it's still the same design, just improved.

AMD on the other hand, has gone through changes over the generations, from the old Athlon/Athlon64, then the X2, Phenom series. They went with Bulldozer(FX series desktop chips), but the IPC wasn't very good compared to Intel, so high clock speed, but poor efficiency. AMD is on the Zen cores now, which are not based on previous designs, and the performance proves that point. A new fab process will improve the implementation, higher clock speeds, lower voltages, or a combination of the two, but no fab process can save a bad design, and fab process improvements won't get around a stagnant design either.

Intel is trying to claim that their only way to improve the design of the Core series is through fab process improvements? Did all the real innovators at Intel die or retire 5+ years ago, since this is NOT a difficult concept. A better design on an old fab process will still be better than a bad design on that old fab process. Clock speeds might be lower, but the DESIGN is key, along with having enough cache to feed the CPU cores. Yes, cache helps, but honestly, Intel BS still stinks.

Re:Finally

[epine]

We're both old timers, but apparently I've kept up better than you have.

First of all, cache (and the rest of the communications fabric) is more than the half the design of a high performance CPU. Long ago now are the days where the core itself was the anchor tenant, and the rest of chip amounted to window dressing. The primacy of the core to the chip (and the ISA to the core) was the central (and false) conceit of the original RISC paradigm. If the window dressing hadn't been more important than they wished to acknowledged, there's a good chance that one of the RISC designs would have succeed in unseating Intel, long ago.

Intel was almost forced into this by accident. Starved of registers in the ISA, but having a tight read/modify/write instruction format that efficiently allowed the local stack to function as an extended register set (more efficiently than for RISC), Intel was forced to accept that their competitive foundation was memory agility (without taking this view, their ISA was the crippling liability all their RISC competitors so loudly proclaimed).

When Intel's first OOO chip came out in the mid 1990s with the first Pentium Pro there was the great day of reckoning in the RISC camp. They had all naively assumed that x86 would never achieve those kinds of performance numbers on heavy, server workloads. RISC people read the numbers and muttered under their breath "oh, shit, we're doomed". And they were right.

RISC still easily won single threaded workloads, and floating point workloads by a factor of 2:1, but on a heavily loaded server, the P6 simply never caved. Small register sets make for faster task switching. Intel had provisioned several layers of cache, with lots of internal concurrency, and an external split-transaction data bus. Departmental file and mail servers all went straight to the P6, while dedicated COTS workstations, especially engineering workstations, went in for Alpha or MIPS (you could obtain Windows NT in a variety of flavours back then). Which market would you rather have? COTS Windows NT workstations were a niche market poaching from Sun's well-defended back yard.

The press roundly thrashed the P6 because it wasn't very good at running Window 95. Talk about short-term small-minded priorities. Meanwhile, it ran 32-bit protected OSes like a champ. Most important chip in Intel's history, in my opinion, and the one true reason why x86.die.die.die never came to pass as confidently foretold by every enlightened RISC chip-head to ever awaken under a juniper bush after eating way too much majestic, desert-sunset peyote.

Except for the Pentium IV debacle, every major chip Intel has released since is basically just a P6 fitted out with a king cab and jacked suspension. AMD kindly contributed an expanded ISA with more and wider registers. Intel gradually provided wider decoders, more dispatch paths, more execution units, more in-flight instructions, better branch prediction, larger TLBs, larger caches, better cache prediction, some fancy new SIMD instructions, etc. but it was all just more of the same.

As the multicore era progressed, an actual new technology was the invisible core added to manage the thermal envelope. This was not something the P6 needed to do. There was no instruction mix that would burn the chip out, if it didn't self limit (though some especially pernicious instruction mixes would separate the men from the boys in your CPU's cooling system.)

This ushered in a new design regime where peak performance (aka bragging rights) had to compromise with performance/watt. Just because a clever design would make some subsystem faster, didn't mean that design would win (you had to also look at the thermal cost). Gradually, the performance/watt criteria became the senior cook in the kitchen.

Performance/watt is joined at the hip with your fabrication node. Modern nodes don't offer just a single transistor dimension, but multiple choices of transistor dimension, depending on whether you wish to emphasize speed or thermal efficie

Re:Finally

[epine]

I should note that the improperly maligned P6 was also trashed by a second camp, the assembly language power optimizers, such as Michael Abrash (though I don't recall his complaints, specifically).

The superscalar Pentium was deterministic. You always got the same clock count from the same initial conditions.

But on the P6, the OOO pipeline has it's own complex internal history, and it inserted random bubbles into the pipeline that no-one ever explained.

The problem with a bubble is that it can knock your instruction decode cadence into a different alignment and that could change dispatch order, and then you'd get weird, fluctuating benchmark scores that would be 2.7 IPC on one pass through the loop, then 2.9 IPC on the next pass through the loop.

People who naturally go into this line of work were almost uniformly more irritated that 2.7 != 2.9 than they were impressed that 2.7 >> 2 (the best IPC the Pentium ever achieved).

Daniel Kahneman could have studied this and included it in Thinking Fast and Slow. It's not just Israeli parole judges suffering from an empty stomach who defy rational comprehension, turns out our own tribe is also far from immune.

Re:Finally

[drinkypoo]

RISC still easily won single threaded workloads, and floating point workloads by a factor of 2:1, but on a heavily loaded server, the P6 simply never caved.

RISC also got its ass whipped hard on [fl]ops/$, and electricity was cheap at the time. There was no significant penalty for doubling up on systems to make up for the performance deficit.

Beyond power management, an additional component of actual innovation on modern server Xeons is the on-chip interconnect fabric. Beyond four cores, this gets much harder, and you start getting ring busses, and other weird shit, none of which Intel has rushed to document. The distributed care and feeding of 24 cores crammed onto a single die with way too few overworked memory channels is among the most proprietary technologies Intel now owns (yeah, that's the memory hierarchy again, isn't it?)

I feel like you left something out here about AMD: HyperTransport. A big part of AMD's clawing its way up out of the muck was inventing a practical high-speed interconnect that scaled to significant numbers of cores.

Fabric is a black art. Core design is almost simple by comparison. The Chinese wouldn't even be able to directly adopt any of the leaked core design, because they wouldn't be able to fabricate the process to which is was painstakingly matched.

That's much of why I believe that if Intel is going to remain relevant going forwards, they're going to have to make process technology a priority again — and further, if they want to compete today they're going to have to demonstrate a willingness to produce other people's products in their fabs. They don't have to be CPUs, though, or at least not flagship ones. There must be other applications which would benefit from an advanced process.

If they build them, we will come

[skovnymfe]

But will they build them?

reaction?

[Hentai007]

When asked for a reaction the HR person just screamed "More" followed by "oh God more" and finished with a long exhale.

Oh yeah...

[MTEK]

Sunny goes Deeper, Wider, and Faster

Confused

[DaMattster]

Okay, I am confused. I thought that Intel was abandoning the 10nm process because of difficulty and cost issues. I was under the impression that they're going right to 7nm fabrication.

Re:Confused

[AHuxley]

A new method got approved and its all good again.

Or design is as good as it can be?

[lamer01]

Have you thought of that? At some point cpus just won't get any faster from a design perspective. Maybe all the patterns and ideas on how to speed up CISC cpus have been tried and this is the best that will ever be. Maybe now, speed increases can only be had by frequency increases and cores. Single core ipc may have reached peak.

Re:Or design is as good as it can be?

[UnknownSoldier]

Single core IPC peaks out around ~5 GHz for Silicon at room temp.

20 years ago there were 500+ GHz CPUs -- they weren't using silicon which means they cost a fortune due to the cooling requirements.

The only way to push past the 5 GHz barrier at room temperature is to find a cheap, replacement for Silicon. That's not going to happen anytime soon.

Re:Or design is as good as it can be?

[An Ominous Cow Erred]

He's saying Instructions Per Clock has peaked, not clock frequency (though silicon clock frequency has been hitting a wall too). Peak IPC is peak IPC whether you run it on 5Ghz silicon for 500Ghz photonics or whatever. The process doesn't matter other than adding/removing some small delays due to speed of light distances and thermal management (and this is combatted with pipelining to semi-mitigate the problem). In the end though there's only so much speculative execution you can do, only so much instruction level parallelism to exploit, etc., it's a matter of diminishing returns and you have to throw more and more logic elements at new attempts to wring out a tiny bit more parallelism and stall prevention for ever-smaller gains.

Any other improvements have to come from completely different computing paradigms like thread-level parallelism (i.e. pre-sorting the work for the ALUs to hit in parallel), or quantum computing (essentially using the multiverse to give you an infinite number of speculative-executing ALUs if you go by the many-worlds interpretation). Standard old single-thread logical execution can only be stretched so far.

Or Metal is as good as it can be?

[Ostracus]

https://pubs.acs.org/doi/10.10...

My wife is very interested in this for some reason

[Anonymous Coward]

Normally she isn't very interested in technology but she can't stop telling her girlfriends about this.