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MIPS Goes Open Source (eetimes.com)
Junko Yoshida, writing for EETimes: Without question, 2018 was the year RISC-V genuinely began to build momentum among chip architects hungry for open-source instruction sets. That was then. By 2019, RISC-V won't be the only game in town. Wave Computing (Campbell, Calif.) announced Monday (Dec. 17) that it is putting MIPS on open source, with MIPS Instruction Set Architecture (ISA) and MIPS' latest core R6 available in the first quarter of 2019. Art Swift, hired by Wave this month as president of its MIPS licensing business, described the move as critical to accelerate the adoption of MIPS in an ecosystem.
Going open source is "a big plan" that Wave CEO Derek Meyer, a MIPS veteran, has been quietly fostering since Wave acquired MIPS Technologies in June, explained Swift. Swift himself is a MIPS alumnus who worked at the company as a vice president of marketing and business development for four years. Wave, which styles itself as a tech startup poised to bring "AI and deep learning from the datacenter to the edge," sees MIPS as a key to advancing Wave's AI into a host of uses and applications. Included in MIPS instruction sets are extensions such as SIMD (single instruction, multiple data) and DSP. Swift promised that MIPS will bring to the open-source community "commercial-ready" instruction sets with "industrial-strength" architecture. "Chip designers will have opportunities to design their own cores based on proven and well tested instruction sets for any purposes," said Swift.
Going open source is "a big plan" that Wave CEO Derek Meyer, a MIPS veteran, has been quietly fostering since Wave acquired MIPS Technologies in June, explained Swift. Swift himself is a MIPS alumnus who worked at the company as a vice president of marketing and business development for four years. Wave, which styles itself as a tech startup poised to bring "AI and deep learning from the datacenter to the edge," sees MIPS as a key to advancing Wave's AI into a host of uses and applications. Included in MIPS instruction sets are extensions such as SIMD (single instruction, multiple data) and DSP. Swift promised that MIPS will bring to the open-source community "commercial-ready" instruction sets with "industrial-strength" architecture. "Chip designers will have opportunities to design their own cores based on proven and well tested instruction sets for any purposes," said Swift.
Not to sound too disparaging. But Open Source is often the waste bin of dead technology.
Well we worked hard on it, it wasn't profitable. Might as well open source it, and see if anyone else would have any value with it.
There are some successes such as Mozilla which Netscape Dumped its Netscape Communicator Code to the Open Source, because they were not making money from it. But there are a lot of other things that just never did anything with. Because it was garbage.
If something is so important that you feel the need to post it on the internet... It probably isn't that important.
SPARC has been GPL for years (Score:?)
by Anonymous Coward on Monday December 17, 2018 @03:51PM
Risc-V never was the only game in town; SPARC has been avaialable under the GPLv2 since 2006: https://en.wikipedia.org/wiki/OpenSPARC
You're missing the big picture here. While SPARC and MIPS lost out to x86 they are both mature ISAs with many competing features to x86. For example they have their own SIMD implementations on the FPU. This will be a big boon to RISCV. One of the places where RISCV will find it hard to compete with x86 and ARM is that they both have some very important patented extensions. Intel beat its competitors not because x86 was technically better, but because they were able to catch the widespread consumer adoption in PCs which lead to them being able to outspend others in process node technology. Now that TSMC has caught up to them a great deal, the only other major performance hurdle are the ISA extensions and optimizations. If MIPS is truly FOSS then many of those mature features can be re-implemented into RISCV and earn a massive performance boost. Specifically the SIMD extensions and VPE (MIPS equivalent to hyper-threading) will be useful.
Does this mean we'll finally get IRIX running on a new system? It'd be cool to get IRIX running on a laptop form factor. Not overly useful but hey Photoshop 3.0 and Maya 6.0 are pretty cool. Plus we can all pretend to be artiste's with Power Animator.
Ideally, we need several.
But to really understand what works and why, you want examples.
I hope, now the Itanium 3 has been discontinued for a while, that and the Intel iWarp are open sourced. Doubt it, but one can always hope.
Between the MIPS, the T2, the GPLed SPARC, the RISC-V, the open source elements of the AMULET series and everything on Open Cores, we've a substantial body of knowledge on very large numbers of threads, very high performance, asynchronous computing and advanced ALU.
Throw in the two above as well and our understanding is almost complete.
It's a small world and it smells funny; I'd buy another if it wasn't for the money; Take back what I paid (SoM)
Well we worked hard on it, it wasn't profitable. Might as well open source it, and see if anyone else would have any value with it.
It's a fair criticism but in this case it's the non-altruistic motive: they want other people to maintain their tech for them.
Wave is a hardware neural net company. They bought MIPS so that they could have an ultra low power CPU to handle the basic overhead of an OS and dispatch training jobs to their custom ASIC. Since the MIPS CPU is nothing more than a necessary evil in their system, open sourcing means they maintain a healthy MIPS ecosystem to keep their CPU architecture from rotting and maybe even evolving. The more people that use their CPU the more free updates they get. Win\Win.
I posted this at hacker news (tl;dr - SPARC and MIPS had design aspects that were great in 1983, but didn't scale): https://www.jwhitham.org/2016/...