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IBM Unveils New Power4 CPU
Climbing out from under my mountain of spagetti code and strange bugs (I think I'm finally on top of it actually) to post linkage to a pretty interesting looking new IBM CPU.
The Power4 processor puts 2 processors and an L2 cache on the same die. Clock speed over a gigahertz and bus speed over 500mhz.
My guess on how CPU's could/should progress:
1a) More than one CPU on same chip (now IBM did it)
1b) CPU's and really good 3d (e.g. TNT2-style)graphics engine on same chip
1c) Reconfigurable computing (Transmeta?)
2) More than one reconfigurable CPU on same chip
3) Large reconfigurable CPU which can divide itself in a way that it becomes several independent CPU's of arbitrary size according to use at the moment.
4) Large reconfigurable CPU with the #4 stuff, but in a 3D design (a cube), once somebody figures out how to layer it and cool it.
Anyway, just some ideas.
Nintendo is going to use a G3(300MHz, IIRC)
Posted by Nr9:
this is a 64 bit implementation of the powerpc chip. power3 and power4 are followups to the PowerPC 620 design(power3 was originally called PowerPC 630). it is simliar in design but i'm not suggesting binary compatiblity with 32 bit powerpc chips like the G4
I was under the impression that PowerPC was a spinoff of the Power2 chip, which was 32bit. I remember having lots of fun when I had an IBM 3BT Power2 at 67MHz and a 43P with a PPC604 running at 133 to play with. Ahh... The good 'ol days of three years ago. :-) At one point they were nice machines, until the 3BT started having power supply problems. The 43P was never good for much other than looking at and using it as an X display terminal (32Mb of RAM).
Russ
Posted by Nr9:
actually shared cache over a fast bus(same die) is very fast
MEMS = Micro Electro-Mechanical Systems. MEMS deals with implementing mechanical and electronic systems together on the same chip using semiconductor manufacturing technologies, like pressure sensors and the related circuitry on the same die, micromirror display technology like TI's DLP(Digital Light Processing). MEMS does not even remotely involve anything like multiple CPUs and networks on a single die.
So "we're not getting closer to the MEMS idea." MEMS is something totally different, out there, and will be a very, very important field in the near future.
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Yes, but I can stick a SCSI tape drive on the back of a running AIX box, run 'cfgmgr' and then use said tape drive.
Jim
This is GREAT! This technology has been rumored to be part of IBM/Mot plans for the generation of PowerPC after G4 (I think it's called V-Ger). This is the first official document that I have seen mention it.
I think the rumor sites have the multi-PowerPC chip slated for 2001/2002... but that's not taking into account the Book-E architecture that they are developing too. That's due around the same time... it's another "wait and see and hope" scenario I guess.
The Power"X" line always gets the cool technologies before they trickle down to PowerPC but at least now I know the plans are definitely in the making.
mmmmmm... multicore PowerPC... mmmm
OS/2 for the PowerPC was released and available for some time. It got killed because of poor demand for the product. About the other ones, well, IBM wasn't alone in their development (Apple and Motorola were there too), so they can't be given all the blame for it.
In Soviet Russia, Jesus asks: "What Would You Do?"
the chips seem to be pretty much the same in as400/rs6k and ppc now, with usually better floating point math in the the rs6k and much higher i/o rates for as400. the power4 chip will probably be made in burlington vermont at some point as they are building a nice new mask house here, and i'm sure it it will also be made in fishkill and/or pokipsie(sp). ps as far as i know gekko is being developed in burlington vt
The biggest difference between the PowerPC (Motorola-made) and Power3/4 chips is instruction set. IBM went for all out, "God on Silicone" power and Motorola did a version of the MMX instruction set for theirs. the IBM's don't have AlteVeca(sp?), so just do straight bruteforce and floating point processing.
This translates into AIX, Linux, and maybe MacOS/OSX. The world doesn't revolve around Intel- and shortly the rest of the world will come to the realization. Merced doesn't run any of the x86 architecture either. The subject becomes moot.
I am not merely a "consumer" or a "taxpayer". I am a Citizen of the State of Texas
Now you've gone and gotten the resident RS/6000 pimp and guru involved.
First off; 500MHz bus is so incredibly easy for IBM to achieve, it's not funny. The problem is that they don't have a matching processor to use 500MHz bus. And 500/2 is NOT 262MHz. And you can't cleanly get 340MHz out of it either. Those speeds correspond to the RS64-II processors housed inside the RS/6000 S70 Advanced Server and the RS/6000 H70, two of the fastest single-system computers in the world.
IBM can do it. They've been doing all that for ages, save for the twin-die. In case all of you have forgotten, IBM/Motorola are now in bed together again. This is a very good thing, seeing as they share the CopperGold patents which are used in the production of all of IBM's PowerPC processors. I suspect it's also used in the motherboard manufacturing process.
Let's do a quick lookover of the RS/6000's I mentioned above; the S70 Advanced Server and the H70 in basic single processor configurations.
SPECint95: N.A. 144
SPECfp95: N.A. 182
OLTP Perf: 46.0 16.7
(N.A. denotes 'Not Available' - The S70AS does not have SPECint/SPECfp results publically available.)
How about handling the web?
In their max configurations.. the S70 Advanced Server with 12 RS64-II's at 262MHz achieves a SPECweb96 ops/sec score of an astounding 20,200.
The H70, with 4 processors, achievs an astounding score of 11,774. Now let's jump ship on the more 'typical' RS/6000's and look at where IBM will more than likely stick this processor first.
The legendary SP2, otherwise known as Deep Thought. Yes, that's right. Deep Thought is available for *retail* sale, and eats no less than 60 spaces on the top 500 supercomputer list, in it's many retail configurations.
A *single* Type 9076 Wide node with dual POWER3 processors running at just 200MHz achieves the unbelievable SPECint95 of 222 and SPECfp95 of 468.
Keep in mind this; these processors are running at just 200MHz. *DEAD* slow for you Intel weenies. Ancient technology, some would say.
Yet they achieve higher SPECint95 and SPECfp95 scores than pIII-Xeon 550's. By far. The single processor configuration achieves int95 of 111 and fp95 of 243. Now, cram 16 of those into a single computer known as the SP2, which is really just an active backplanar chassis. Realize the performance increase is a 'pure' curve; each wide node added is worth a SPECint95 score of 111 and a SPECfp95 score of 243. 16 of those give you an overall SPECint95 score of 1776 and an overall SPECfp95 score of 3888. That's 16 200MHz processors with 256M of memory per processor and 4M of L2.
IBM can do it, and deliver on it by the end of December if they wanted to! IBM knows what they're doing, and knows what they're saying. IBM doesn't do vaporware. They said OS/2 Warp 5 was going into beta months ago. Two weeks after they said that, I recieved my beta CDs. When they say they'll have a fix for an AIX problem within a week, you have it within a week.
IBM doesn't deliver vaporware; they deliver promises. Clouds with a silver lining, if you will, since this means that Motorola also gets access to this technology. (Assuming I understand their current pact correctly.) Who wants to jump the x86 ship with me now?
-RISCy Business | Rabid System Administrator and BOFH
your company here.
shelby != ford
i.e. a plug-in LAN on a motherboard.
What exactly would be the advantage of having a plu-in LAN on a die? Why would you want to network with yourself?
If I'm way off, please let me know. I didn't quite understand that point.
Insert mind here.
That should be on the horizon for consumer type people soon, if it hasn't happened already in a manner of speaking. Right now things such as 3D now and other SIMD extensions are additional processing power and are quite close to having an additional processor on the same die. They accelerate a sub genus of instructions much like math coprocessors did in the 80's to early 90's. They've of course been assimilated into the main core for quite some time now as well.
If Moore's law holds out by 2010 we'll have approximately 8 times the number of transistors in a socket as we do presently. So instead of ~20 million it'll be around ~160 million. That's a lot of transistors. More massive onchip cache will be one of the first improvements and maybe a moderate bump in bus width. I say only a moderate increase because more density on a motherboard is expensive and isn't scaling at the same speed as circuit density. Chances are you'll see 2 or 4 way SMP on consumer processors instead. You also might see true system integration: RAM, ROM, CPU and graphics subsystems etc, this would be for what is now the sub 1000 dollar market.
Hmmm - doesn't that put
Linux = software crop von the....
Er... let's not go there...
Posted by Nr9:
it doesn't need to waste a lot of cycles doing it.. just used the same as normal L2 cache
At last, that AS400 laptop I've been dreaming of!
I see even classic Slashdot is now pretty much unusable on dial up anymore.
IBM's processor stuff looks good on paper, alone, but they are not anywhere near leading the pack -- especially for integers. The Alpha and HP PA-RISC processors are where you find top notch speed. Last I heard, IBM can't even do SMP with more than 12 processors. Don't respond with IBM SPs...I said SMP.
I'm won't even touch the price/performance ratio of IBM gear.
...doing the fabs for transmeta?
s/[BW]ill(y|iam)?( H\.?)?( G(ate|8)(s|z))?(,? ?v?(III|3)(\.\D)?)?/Girly-man/gi
What kind of operating systems will we be able to run on this new chip? I'd hate to see such wondrous technology squandered by the need for new proprietary software.
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Wow.. a cool new brain for use in a Mac! Pop one of those on a ZIF card and shove it in my aging beige G3 box.. can't wait =)
-----
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Those who laugh at you for you having a Mac.. are the people who constantly call you to fix their PC.
First rule of responsible journalism: Don't provide free advertising by printing a press release as a real story.
/. itself) could do to salvage the situation is to print "IBM claims that..." before stories like this and track them all with hit/miss stats given. That way there would be less "free advertising" incentive because if they over-promised and under-delivered they'd be caught out.
Example: "The processor will be used in both the AS400 and RS/6000 server families, which are slated to hit the market in 2001."
In other words: "Even in our wildest dreams this product won't be available for at least 18 months and that's real time, not Internet time."
That's not an "exciting new product", that's a load of crap. I used to watch Beyond 2000 and other programs that "showcase new technology" until I realized that the promises of "you'll see it in 3-5 years" never came true. Same thing here.
What this fellow (not to mention
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I agree 100%. I've spent about 5 years total contracting in and out of IBM Austin's RS/6000 divisions (AIX defect support, CPU stress test, and some early web development) and was very impressed with every department I spent time with.
In the hardware labs (back in '91) I was like a kid in a candy store; the early 320, 520 and 530 was rolling through and at the time were sweet boxes. I think the processor planar on the 320 ran at 37mhz, but smoked 100mhz Pentiums in floating point and integer.
The data path between the CPU/data/instruction cache were a whopping 288 bits (on the ancient 340s).
Way back in '91 they were working on a split transaction crossbar buss for the upcoming SMP systems which I think turned into the J30.
Throw AIX in the mix with all its cool features and you have a nice rock solid system.
Jim
1) Do POWER processors have an integrated FPU? If
so, does this 2-CPU on a die have a
shared FPU or 2 separate FPUs?
2) Is it possible and/or likely that they might
share certain components without
performance degradation?
3) Does this use the copper fab stuff that IBM
announced some time ago?
For every problem, there is at least one solution that is simple, neat, and wrong.
If you check this page....
3 p_260_specs.html
http://www.rs6000.ibm.com/hardware/workgroups/4
You'll see that they really only do about 13.2 SPECint, and 30 SPECfp. The "rate" numbers can't be compaired with normal SPEC numbers...
Power is the parent, PPC is the child. Or in other words, the PPC series were started by taking the Power architecture and simplifying it a lot.
The first PowerPC chip to ever come out, the PPC 601, actually had a larger instruction set than what the more recent PPC chips have. The compilers of the time were optimized for the larget instruction set of the Power architecture and the first Mac PPC programs couldn't be used on the 604 and 603 as they weren't 100% binary compatible.
--sulka
"Although it is not true that all conservatives are stupid, it is true that most stupid people are conservative."
Sorry, but their processors work just fine. The point being that integer crunching is not the focus of business machines, and never will be.
Hence while IBM succeeds with in business all these other companies spout their "crunch" capability and wonder why business doesn't care.
Sometimes its not how much you do, but what you do.
Besides, if you want a reliable server you use an AS/400. (which has been 64bit for some time now - oh lest I forget - to go from 32bit to 64bit did not require rewrites on 99% of software???)
. * Did aliens forget to remove your anal probe?
POWER3 is a 64-bit PowerPC chip. The PowerPC family of processors was designed from the ground up with 32-bit and 64-bit binary compatibility. Code compiled for a POWER3 will run on a PPC 750, albiet a bit slower since the PPC 750 was not designed with 64-bit words in mind. (32-bit code will also run slower than 64-bit code on a POWER3, so it's not that more bits is faster.) However, all the instructions that work with 32-bit and 64-bit values are implemented in both 32-bit and 64-bit silicon, I believe. Of course, the 64-bit / 32-bit deal is just over integers. The FPU on both series of chips is 64-bits.
This is fruition of the G2K project that Motorola and IBM were working together on before the split over Altivec. Multiple processor cores on a single chip and 1 GHz speeds were their goals for that project. While the 500 MHz memory bus is probably a long way off from coming to Macs due to the expense, I wouldn't be too sure that a multi-core G4 is so far away from being in Macs.
If it's for-profit but free, you're not the customer -- you're the product (e.g., the Slashdot Beta's "audience").
IBM has been working on this for at least 3 years already. I remember back when the G3s were just a product plan, that the AIM map for the PPC family included the G2K project which included such features as multi-core PPCs and 1GHz operating speeds. The 1.1 GHz chip demoed over a year ago was part of the fruition of that project.
This is IBM, not Intel. They are one of the more conservative corporations about press releases. This targetted release date is exactly consistent with the estimates that the G2K project had projected 3 years ago -- that they would have test chips in 2000 and production silicon by 2001. Compare this to the ever shifting projections for the IA-64 family's debut.
If it's for-profit but free, you're not the customer -- you're the product (e.g., the Slashdot Beta's "audience").
There is an excellent article in this month's Performance Computing (from the Unix Review) about the roadmap IBM has leading up to the Power4..
Plus there's a super whizzy electron scan cross section of a chip built using IBMs new SOI chip process which basically builds the transistors with a small substrate of Silicone Dioxide on top of an insulator which sits on top of the silicon wafer. Apparently, the bigger the piece of silicon you use for the transistors, the more capacitance it has, and the more energy it takes to charge/discharge the transistor, so these new chips take less power and can be packed closer... Hope I'm getting some of these technical details right...
Anyway, basically IBM is using it's way-better-than-everyone-else chip manufacturing technology to kick some major butt. This thing looks sweet. One thing not mentioned here (at least I didn't see it) is that because they're gonna bump up to 1 GHz, they had to lengthen the pipeline -> each instruction may take more clock cycles now. What they were doing to compensate was to make the chip able to run instructions out-of-order, beefing up the code branching analysis, and adding an L3 cache (off the die) to improve memory performance.
Well, in the Performance Computing Article I read, it said that IBMs current processors have 15 million and 12 million transistors... The Power4 is supposed to have 170 million... fun, huh?
Does it run Windows?
Fact 1: Yellowdog is working on supporting the current generation of RS/6000 machines. Fact 2: IBM has an ingrained perpensity to slap a slab of monolithic microcode over the hardware. (So they don't lose any of the legacy software market with their new products) Conclusion: We may be able to run Linux on this new Power4 beast. A sixteen way Linux box that could recompile its own kernel a thousand times a second.. My knees are weak...
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No. Its a 64 bit PowerPC chip. No Windows there.
Andrew Gardner
Outside of a dog, a book is a man's best friend. Inside a dog, its too dark to read.
Heh why not? Add a new device...no downtime for kernel recompile. Perhaps AIX is a bit over-engineered...but I'm not complaining.
Blar.
Although pervious posts seem to conclude that the Power and PowerPC lines are different, the designs seem remarkably similar - multiple processor cores, large L2 caches, good SMP support... Does anyone know exactly how similar these two processors really are, and whether or not a variant of LinuxPPC could be run on such a beast?
just my blog and pix
If there's one thing I know, it's that management never learns from it's mistakes.
See, I work for a fairly successful company (which shall remain nameless) that just upgraded to the 12-way RISC, and is gambling on this next 400 to be there when we outgrow the new one in 2 years.
The problem is, the last time they took this gamble, IBM promised and promised but nothing showed up in time. We were forced to Opti-connect 2 boxes together just to get by.
The biggest mistake in this gamble now is that they got rid of the Opti-connect environment when they upgraded! What a mess! At least if they continued testing for Opti, we would have some sort of failsafe but they nixed that too.
So now when IBM fails to come through again we're dead!
After all, management sure isn't gonna take the blame.
Can a AA battery handle 50+W worth of power? :)
SPECint95 rating of 111 for 1 200MHz CPU? You must be dreaming. The highest official single-CPU SPECint95 ratings belong to the Compaq XP1000 with 37.5 (1 x 21264A CPU at 667MHz) . Be careful with that stuff you've been smoking.
"I love my job, but I hate talking to people like you" (Freddie Mercury)
Darn! I was just going to ask on Ask Slashdot when we'd be getting SMP-on-a-chip, seeing as it *is* the natural progression (more so IMO than video and sound integration, but don't get me started on that :)
Anyhow, this is not i386, so I still ask: does anyone anywhere have any idea when i386 (be that ia32 or ia64 or...) will show its ugly face in SMP-on-a-chip congigurations?